T7115AMCD LSI, T7115AMCD Datasheet - Page 23

• Manufacturer Part Number: T7115AMCD
• Manufacturer: LSI

Specifications of T7115AMCD

• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

Data Sheet
April 1997
Functional Description
Programming Note: Since the receiver writing to the
receive FIFO and the host reading from the receive
FIFO are asynchronous events, it is possible for a host
read to put the number of bytes in the receive FIFO just
below the programmed RIL level and a receiver write to
put it back above the RIL level. This causes a new RF
interrupt. This has the potential to cause software prob-
lems. It is recommended that during service of the RF
interrupt, the RF interrupt be masked RFIE (R14—B3)
= 0 and the interrupt register be read at the end of the
service routine, discarding any RF interrupt seen,
before unmasking the RF interrupt.
Programming Note: After the transmitter is turned off,
a transmitter reset should be performed (TRES, R6, bit
5 = 1) before the transmitter is turned on. After the
receiver is turned off, a receiver reset should be per-
formed (RRES, R6, bit 4 = 1) before the receiver is
turned on. The transmitter and receiver should both be
reset individually (i.e., not at the same time) after any
concentration highway configuration change. If TRES =
RRES = 1 at the same time, a full chip reset is per-
formed: all register bits are forced to their reset values.
Receiver Overrun
A receiver overrun occurs if the 64-byte limit of the
receiver FIFO is exceeded, i.e., data has been received
faster than it has been read out of the receive FIFO and
written to the system memory. Upon overrun, an SF
status byte with the overrun bit (bit 5) set replaces the
last byte in the FIFO. The SF status byte can have
other error conditions present. For example, it is
unlikely the CRC is correct. Thus, care should be taken
to prioritize the possible frame errors in the software
service routine. The last byte in the FIFO is overwritten
with the SF status byte regardless of the type of byte
(data or SF status) being overwritten. The overrun con-
dition is reported in register 15 (R15—B5) and causes
the interrupt pin to be asserted if it is not currently
asserted and it is not masked (ROVIE, R14—B5). Data
is ignored until the condition is cleared. The overrun
condition is cleared by reading register 15 and reading
at least 1 byte from the receive FIFO. Because multiple
frames can be present in the FIFO, good frames as
well as the overrun frame can be present. The host can
determine the overrun frame by looking at the SF sta-
tus byte.
Lucent Technologies Inc.
(continued)
Operational Note (T7121-EL, T7121-PL, T7121-EL2,
and T7121-PL2)
In HDLC protocol, binary 1s may be transmitted
between frames (interframe fill) when no user data is
available. Short bursts of interframe fill, not specified in
the current standards, have been encountered when
system testing against some switch equipment. Per
Lucent’s interpretation of the standards, the device will
treat received interframe fill from 1 bit to 5 bits in length
as a short packet and report a received end of frame
condition in register R15, bit 4 (EOF = 1). A hardware
interrupt will be generated if the REOF interrupt is
enabled in register R14, bit 4 (REOFIE = 1). This may
be a performance issue in some systems due to the
extra interrupts that the host processor must service,
produced by short bursts of interframe fill from 1 bit to
5 bits in length.
The contents of both register R4 (Receiver Status Reg-
ister) and the receive FIFO depend on the number of
interframe 1s received.
If one bit of interframe fill is received, R4 will indicate
that an end of frame has occurred, but zero bytes are
stored in the receive FIFO (i.e., no Status of Frame
byte was written to the FIFO). Data reception can pro-
ceed normally without further intervention by the host
processor.
If 2 bits to 5 bits of interframe fill are received, R4 will
indicate that an end of frame has occurred, and that
one byte was stored in the receive FIFO. The 1 byte
stored in the FIFO is the Status of Frame byte due to
the interframe fill and will have a value of 0x90, indicat-
ing a bad CRC and bad byte count. This byte should be
read out and discarded. After removing the Status of
Frame byte from the FIFO, data reception can proceed
normally without further intervention by the host micro-
processor.
If 6 bits or more of interframe fill are received, the
device correctly ignores these bits. The FIFO is not
written and no interrupts are generated.
T7121 HDLC Interface for ISDN (HIFI-64)
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