STM32L152-SK/IAR STMicroelectronics, STM32L152-SK/IAR Datasheet - Page 14

• Manufacturer Part Number: STM32L152-SK/IAR
• Description: MCU, MPU & DSP Development Tools STM32L152VBT6 IAR 32KB Workbench
• Manufacturer: STMicroelectronics
• Series: IAR Kickstartr
• Type: MCUr

Specifications of STM32L152-SK/IAR

• Contents: Board, CD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: STM32L

Functional overview
Note:
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The RTC, the IWDG, and the corresponding clock sources are not stopped by entering the
Stop or Standby mode.
ARM
The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The memory protection unit (MPU) improves system reliability by defining the memory
attributes (such as read/write access permissions) for different memory regions. It provides
up to eight different regions and an optional predefined background region.
Owing to its embedded ARM core, the STM32L15xxx is compatible with all ARM tools and
software.
Nested vectored interrupt controller (NVIC)
The ultralow power STM32L15xxx embeds a nested vectored interrupt controller able to
handle up to 45 maskable interrupt channels (not including the 16 interrupt lines of
Cortex™-M3) and 16 priority levels.
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This hardware block provides flexible interrupt management features with minimal interrupt
latency.
Standby mode, the RAM and register contents are lost except for registers in the
Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc, RCC CSR).
The device exits the Standby mode in 60 µs when an external reset (NRST pin), an
IWDG reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or
Alarm B), RTC tamper event, RTC timestamp event or RTC Wakeup event.
Standby mode consumptions: refer to
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Allows early processing of interrupts
Processing of late arriving, higher-priority interrupts
Support for tail-chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
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Cortex™-M3 core with MPU
Doc ID 17659 Rev 4
Table
19.
STM32L151xx, STM32L152xx