A3PE-BRD600-SKT MICROSEMI, A3PE-BRD600-SKT Datasheet - Page 29

• Manufacturer Part Number: A3PE-BRD600-SKT
• Description: MCU, MPU & DSP Development Tools ProASIC3/E Starter Kit
• Manufacturer: MICROSEMI

Specifications of A3PE-BRD600-SKT

• Processor To Be Evaluated: ProASIC3/E
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

LVDS Signal Evaluation
Introduction
Test Setup
Hardware
Design
ProASIC3/E Starter Kit User’s Guide and Tutorial
Due to concerns about the Proasic3 Dev-Kit board layout with respect to the LVDS signaling, the Applications
Consulting group took initiative to evaluate the LVDS signaling on the board. The performance criteria of the board
with respect to LVDS signaling is set to 300 Mb/s per product marketing.
This document explains the test setup and design. It reports the measurements performed on the board, and at the end,
makes recommendations to increase the LVDS signal quality in order to meet the performance criteria.
The test setup uses a ProASIC3 Dev-Kit containing an A3PE600-PQ208 engineering sample. LVDS loopback is
closed using various lengths of CAT-5E cables (1-, 3-, and 6-foot). The measurements are taken using a 1159A-1GHz
Agilent differential probe.
Figure 5-1 on page 29
Proasic3 FPGA. As shown in
(channel A) is driven by PLL to achieve high data rates, and the other (channel B) uses an external clock in case slow
data rates are needed for test or debugging purposes.
Each channel uses an LFSR to generate a pseudo-random data stream. The data stream is entered in DDR registers to
achieve higher data rates from relatively slower clocks (e.g., 300 Mb/s data rate from 150 MHz clock). The output of the
DDR registers is sent out using the LVDS I/O standard. The output data is looped back and received by the FPGA
using LVDS receivers.
CLK_2
CLK_1
shows the block diagram of the transmitter section of the test design programmed inside the
PLL
Figure 5-1 on page
Figure 5-1. TX Portion of Test Design
clk
clk
clk
clk
LFSR_1
LFSR_2
LFSR_1
LFSR_2
29, the design contains two similar channels of data. One channel
out
out
out
out
Qr
Qr
Qf
DDR-REG
Qf
DDR-REG
Dout
Clk
Clk
Dout
Channel A
Channel B
5
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