PIC24FJ32GA002-I/SO Microchip Technology Inc., PIC24FJ32GA002-I/SO Datasheet - Page 133

• Manufacturer Part Number: PIC24FJ32GA002-I/SO
• Description: MCU, 16-Bit, 28-Pin, 32KB Flash, 8KB RAM, 21 I/O, Nanowatt
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ32GA002-I/SO

• A/d Inputs: 10 Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/UART
• Memory Capacity: 32 Kbytes
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Inputs: 21
• Number Of Pins: 28
• Package Type: 28-pin SOIC
• Programmable Memory: 32K Bytes
• Ram Size: 8K Bytes
• Speed: 32 MHz
• Timers: 5-16-bit
• Voltage, Range: 2-3.6 V
• Voltage, Rating: 2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

13.4
REGISTER 13-1:
© 2007 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13
bit 12-5
bit 4
bit 3
bit 2-0
Note 1:
U-0
U-0
—
—
2:
Output Compare Register
RPORx (OCx) must be configured to an available RPn pin. For more information, see Section 9.4
“Peripheral Pin Select”.
OCFA pin controls OC1-OC4 channels. OCFB pin controls the OC5 channel.
Unimplemented: Read as ‘0’
OCSIDL: Stop Output Compare x in Idle Mode Control bit
1 = Output Compare x will halt in CPU Idle mode
0 = Output Compare x will continue to operate in CPU Idle mode
Unimplemented: Read as ‘0’
OCFLT: PWM Fault Condition Status bit
1 = PWM Fault condition has occurred (cleared in HW only)
0 = No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111)
OCTSEL: Output Compare x Timer Select bit
1 = Timer3 is the clock source for Output Compare x
0 = Timer2 is the clock source for Output Compare x
Refer to the device data sheet for specific time bases available to the output compare module.
OCM2:OCM0: Output Compare x Mode Select bits
111 = PWM mode on OCx, Fault pin, OCFx, enabled
110 = PWM mode on OCx, Fault pin, OCFx, disabled
101 = Initialize OCx pin low, generate continuous output pulses on OCx pin
100 = Initialize OCx pin low, generate single output pulse on OCx pin
011 = Compare event toggles OCx pin
010 = Initialize OCx pin high, compare event forces OCx pin low
001 = Initialize OCx pin low, compare event forces OCx pin high
000 = Output compare channel is disabled
U-0
U-0
—
—
OCxCON: OUTPUT COMPARE x CONTROL REGISTER
HC = Hardware Clearable bit
W = Writable bit
‘1’ = Bit is set
OCSIDL
R/W-0
U-0
—
R-0, HC
OCFLT
PIC24FJ64GA004 FAMILY
U-0
Preliminary
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
OCTSEL
R/W-0
U-0
—
(1)
(2)
(2)
OCM2
R/W-0
U-0
—
(1)
x = Bit is unknown
OCM1
R/W-0
U-0
—
(1)
DS39881B-page 131
OCM0
R/W-0
U-0
—
bit 8
(1)
bit 0