MAX1997ETJ Maxim Integrated Products, MAX1997ETJ Datasheet - Page 11

• Manufacturer Part Number: MAX1997ETJ
• Description: LCD Drivers
• Manufacturer: Maxim Integrated Products

Specifications of MAX1997ETJ

• Dc: 0618
• Lead Free Status / Rohs Status: No

Quintuple/Triple-Output TFT LCD Power Supplies
MAX1997
10
11
12
13
14
15
16
17
18
4
5
6
7
8
9
PIN
MAX1998
10
—
—
—
—
—
—
2
3
4
5
6
7
8
9
______________________________________________________________________________________
with Fault Protection and VCOM Buffer
NAME
DRVN
OUTB
DRVA
FBNB
V
FBPB
ONN
GND
ONP
ON2
FBN
FB1
REF
FB2
CT
DDB
Logic Linear-Regulator (REG 1) Feedback Input. FB1 regulates at 1.25V nominal. Connect
FB1 to the center tap of a resistive voltage-divider between the REG 1 output and the analog
ground (GND) to set the output voltage. Place the resistive voltage-divider close to the pin.
Sequence Timing Control Input. Connect a capacitor from this pin to GND. This timing
capacitor controls the turn-on of REG P, REG N, REG 2, and DRVA. The sequence timing
block is enabled, together with the main step-up regulator, when ONDC goes high. Then an
internal 5µA current source charges the timing capacitor from 0V to V
on delay. A discharge switch keeps CT at GND when the sequence timing block is disabled.
(See the Power-Up Sequencing and Inrush Current Control section.)
Gate-Off Linear-Regulator (REG N) Sequence Control Input. REG N is enabled when SHDN is
high, the gate to the input P-channel MOSFET is low, ONDC is high, and V
the Power-Up Sequencing and Inrush Current Control section.)
Gate-On Linear-Regulator (REG P) Sequence Control Input. REG P is enabled when SHDN is
high, the gate to the input P-channel MOSFET is low, ONDC is high, and V
the Power-Up Sequencing and Inrush Current Control section.)
Gamma Linear-Regulator (REG 2) Sequence Control Input. REG 2 is enabled when SHDN is
high, the gate to the input P-channel MOSFET is low, ONDC is high, and V
also controls the DRVA open-drain output, which is typically used to turn on an N-channel
MOSFET between the step-up regulator output and the source driver ICs’ supply pins. (See
the Power-Up Sequencing and Inrush Current Control section.)
Gate-Off Linear-Regulator (REG N) Base Drive. Open drain of an internal P-channel MOSFET.
Connect DRVN to the base of an external NPN linear regulator pass transistor. (See the Pass
Transistor Selection section.)
G ate- Off Li near - Reg ul ator ( RE G N ) Feed b ack Inp ut. FBN r eg ul ates to 125m V nom i nal . C onnect
FBN to the center tap of a r esi sti ve vol tag e- d i vi d er b etw een the RE G N outp ut and the r efer ence
vol tag e ( RE F) to set the outp ut vol tag e. P l ace the r esi sti ve vol tag e- d i vi d er cl ose to the p i n.
Open-Drain Sequence Output. The DRVA open-drain output is controlled by ON2. DRVA is
typically used to turn on an N-channel MOSFET between the step-up regulator output and the
source-driver ICs’ supply pins. DRVA is high impedance when SHDN is high, the gate to the
input P-channel MOSFET is low, ONDC is high, and V
to ground. (See the Power-Up Sequencing and Inrush Current Control section.)
Internal Reference Bypass Terminal. Connect a 0.22µF ceramic capacitor from REF to the
analog ground (GND). External load capability is at least 75µA.
Analog Ground.
VCOM Buffer Inverting Input. (See the VCOM Buffer section.)
VCOM Buffer Output. Requires a minimum 0.47µF ceramic filter capacitor to GND. Place the
capacitor as close as possible to OUTB.
VCOM Buffer Supply Input. Bypass to GND with a 0.47µF capacitor as close as possible to
the pin.
VCOM Buffer Noninverting Input. (See the VCOM Buffer section.)
Gamma Linear-Regulator (REG 2) Feedback Input. FBP regulates to 1.25V nominal. Connect
FB2 to the center tap of a resistive voltage-divider between the REG 2 output and the analog
ground (GND) to set the output voltage. Place the divider close to the pin.
FUNCTION
Pin Description (continued)
CT
> V
ON2
. Otherwise, DRVA connects
IN
, which sets the turn-
CT
CT
CT
> V
> V
> V
ONP
O N N
O N 2
. (See
. ON2
. (See
11