EVALADG888EB Analog Devices Inc, EVALADG888EB Datasheet - Page 12

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EVALADG888EB

Manufacturer Part Number
EVALADG888EB
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of EVALADG888EB

Lead Free Status / Rohs Status
Not Compliant
ADG888
OUTLINE DIMENSIONS
(BALL SIDE DOWN)
BALL 1
IDENTIFIER
TOP VIEW
INDICATOR
1.00
0.85
0.80
PIN 1
0.15
0.05
12° MAX
SEATING
PLANE
4.50
4.40
4.30
PIN 1
Figure 28. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Figure 27. 16-Lead Thin Shrink Small Outline Package [TSSOP]
2.06
2.00 SQ
1.94
BSC
0.65
Figure 26. 16-Ball Wafer Level Chip Scale Package [WLCSP]
BSC SQ
16
VIEW
1
4.00
TOP
COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
0.80 MAX
0.65 TYP
COMPLIANT TO JEDEC STANDARDS MO-153-AB
5.10
5.00
4.90
0.10
0.30
0.23
0.18
4 mm × 4 mm Body, Very Thin Quad
Dimensions shown in millimeters
Dimensions shown in millimeters
Dimensions shown in millimeters
0.30
0.19
BSC SQ
0.20 REF
3.75
9
8
Rev. A | Page 12 of 16
1.20
MAX
SEATING
PLANE
6.40
BSC
0.05 MAX
0.02 NOM
(CP-16-4)
(RU-16)
0.28
0.24
0.20
(CB-16)
0.65
0.59
0.53
0.50
BALL
PITCH
0.65 BSC
SEATING
PLANE
0.60 MAX
COPLANARITY
0.20
0.09
0.75
0.60
0.50
0.08
12
9
0.36
0.32
0.28
13
8
(BOTTOM VIEW)
EXPOSED
0.60 MAX
PAD
0.11
0.09
0.07
16
5
1
1.95 BSC
4
D
0.75
0.60
0.45
0.25 MIN
2.25
2.10 SQ
1.95
PIN 1
INDICATOR
BOTTOM VIEW
(BALL SIDE UP)
C
B
A
2
3
4
1