LM5068MM-2/HALF National Semiconductor, LM5068MM-2/HALF Datasheet - Page 17

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LM5068MM-2/HALF

Manufacturer Part Number
LM5068MM-2/HALF
Description
Manufacturer
National Semiconductor
Datasheet

Specifications of LM5068MM-2/HALF

Lead Free Status / Rohs Status
Supplier Unconfirmed
Timing Diagrams
During normal operation, if the OV pin exceeds OV HIGH, as
shown at time point 1 in the above diagram, the TIMER
status is unaffected. The GATE and PWRGD ( for LM5068-1
& -2) pins are pulled low and the load is disconnected. At
(Continued)
FIGURE 7. Over-Voltage Timing Behavior
17
time point 2, OV recovers and drops below the OV LOW
threshold, the GATE start-up cycle begins. If the load capaci-
tor is completely depleted during OV conditions, a full
start-up cycle is initiated.
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