PPC405GP-3BE266C Applied Micro Circuits Corporation, PPC405GP-3BE266C Datasheet - Page 31

• Manufacturer Part Number: PPC405GP-3BE266C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC405GP-3BE266C

• Family Name: 405GP
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 266MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 2.5V
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 456
• Package Type: EBGA
• Lead Free Status / Rohs Status: Not Compliant

Revision 2.05 – August 19, 2008
Signal Functional Description
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 29.
AMCC
Ethernet Interface
EMCMDIO[PHYMDIO]
PCIGnt0[Req]
Signal Name
EMCTxD3:0
PHYRxD3:0
EMCMDClk
PCIGnt1:5
PHYRxClk
PHYRxDV
EMCTxErr
PHYRxErr
EMCTxEn
PHYTxClk
PHYCrS
PHYCol
Data Sheet
Gnt0 when internal arbiter is used
or
Req when external arbiter is used.
Used as PCIGnt1:5 output when internal arbiter is used.
Received data. This is a nibble wide bus from the PHY. The data is
synchronous with the PHYRxClk.
Transmit data. A nibble wide data bus towards the net. The data is
synchronous to the PHYTxClk.
Receive Error. This signal comes from the PHY and is synchronous
to the PHYRxClk.
Receiver Medium clock. This signal is generated by the PHY.
Receive Data Valid. Data on the Data Bus is valid when this signal is
activated. Deassertion of this signal indicates end of the frame
reception.
Carrier Sense signal from the PHY. This is an asynchronous signal.
Transmit Error. This signal is generated by the Ethernet controller, is
connected to the PHY and is synchronous with the PHYTxClk. It
informs the PHY that an error was detected.
Transmit Enable. This signal is driven by the EMAC to the PHY. Data
is valid during the active state of this signal. Deassertion of this signal
indicates end of frame transmission. This signal is synchronous to
the PHYTxClk.
This clock comes from the PHY and is the Medium Transmit clock.
Collision signal from the PHY. This is an asynchronous signal.
Management Data Clock. The MDClk is sourced to the PHY. This
clock has a period of 400ns, adjustable via EMAC0_STACR[OPBC].
Management information is transferred synchronously with respect to
this clock.
Management Data Input/Output is a bidirectional signal between the
Ethernet controller and the PHY. It is used to transfer control and
status information.
(Part 2 of 8)
Description
405GP – Power PC 405GP Embedded Processor
I/O
I/O
O
O
O
O
O
O
I
I
I
I
I
I
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
3.3V PCI
3.3V PCI
Type
Notes
1
6
1
1
1
1
6
6
1
1
1
31