PPC405GP-3BE133C AMCC [Applied Micro Circuits Corporation], PPC405GP-3BE133C Datasheet
PPC405GP-3BE133C
Related parts for PPC405GP-3BE133C
PPC405GP-3BE133C Summary of contents
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... UART and memory - Scatter-gather chaining supported - Four channels Description Designed specifically to address embedded applications, the PowerPC 405GP (PPC405GP) provides a high-performance, low-power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation requirements. This chip contains a high-performance RISC ...
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... Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 I/O Specifications—All speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 I/O Specifications—133 and 200MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 I/O Specifications—266MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 PPC405GP Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2 Revision 2.03 – September 7, 2007 Data Sheet AMCC ...
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... Revision 2.03 – September 7, 2007 Data Sheet Figures PPC405GP Embedded Controller Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 25mm, 413-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 27mm, 456-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 35mm, 456-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5V-Tolerant Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 AMCC 405GP – Power PC 405GP Embedded Processor ...
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... Power PC 405GP Embedded Processor Ordering, PVR, and JTAG Information 1, 2 Product Name Order Part Number PPC405GP PPC405GP-3BE133C PPC405GP PPC405GP-3BE133CZ PPC405GP PPC405GP-3DE133C PPC405GP PPC405GP-3DE133CZ PPC405GP PPC405GP-3FE133C PPC405GP PPC405GP-3FE133CZ PPC405GP PPC405GP-3KE133C PPC405GP PPC405GP-3KE133CZ PPC405GP PPC405GP-3BE200C PPC405GP PPC405GP-3BE200CZ PPC405GP PPC405GP-3DE200C PPC405GP PPC405GP-3DE200CZ ...
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... Package B: 35mm, 456 E-PBGA D: 27mm, 456 E-PBGA E: 25mm, 413 E-PBGA F: 35mm, 456 E-PBGA lead-free K: 27mm, 456 E-PBGA lead-free AMCC 405GP – Power PC 405GP Embedded Processor PPC405GP-3BE266Cx Shipping Package Blank = Tray Z = Tape and reel Operational Case Temperature Range (-40°C to +85°C) Processor Speed ...
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... Arb Code Decompression (CodePack™) SDRAM Controller 13-bit addr 32-bit data The PPC405GP is designed using the IBM blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent way to create complex ASICs using IBM CoreConnect 6 OCM Power SRAM Mgmt DCRs ...
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... The PPC405GP incorporates two simple and separate address maps. The first address map defines the possible use of address regions that the processor can access. The second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running on the PPC405GP processor through the use of mtdcr and mfdcr instructions. ...
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Power PC 405GP Embedded Processor DCR Address Map 4KB Device Configuration Registers Function 1 Total DCR Address Space By function: Reserved Memory Controller Registers External Bus Controller Registers Decompression Controller Registers Reserved On-Chip Memory Controller Registers Reserved PLB ...
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Revision 2.03 – September 7, 2007 Data Sheet On-Chip Memory (OCM) The OCM feature comprises a memory controller and a one-port 4KB static RAM (SRAM) accessed by the processor core. Features include: • Low-latency access to critical instructions and data ...
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... Supports PowerPC processor boot from PCI memory SDRAM Memory Controller The PPC405GP Memory Controller core provides a low latency access path to SDRAM memory. A variety of system memory configurations are supported. The memory controller supports up to four physical banks 256MB per bank are supported maximum of 1GB. Memory timings, address and bank sizes, and memory addressing modes are programmable ...
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Revision 2.03 – September 7, 2007 Data Sheet • Peripheral Device pacing with external “Ready” • External master interface - Write posting from external master - Read prefetching on PLB for external master reads - Bursting capable from external master ...
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Power PC 405GP Embedded Processor IIC Bus Interface • Compliant with Philips® Semiconductors I • Operation at 100kHz or 400kHz • 8-bit data • 10- or 7-bit address • Slave transmitter and receiver • Master transmitter and receiver ...
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Revision 2.03 – September 7, 2007 Data Sheet Universal Interrupt Controller (UIC) The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between the various sources of interrupts and the local PowerPC processor. Features include: • Supports seven ...
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... SOLDER BALL x 413 A 14 Part Number 15.7 MAX 25.0 22.0 1.00 ± 0 0.539 REF ∅ 0. ∅ 0. Revision 2.03 – September 7, 2007 Data Sheet Logo View ® PPC405GP 1YWWZZZZZ CCCCCCC Lot Number C 0.20 C 0.25 C 0.35 C 2.223 REF GLOB TOP 0.1 TYP AMCC ...
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... SOLDERBALL x 456 AMCC 405GP – Power PC 405GP Embedded Processor Part Number 24 TYP A 27.0 25.0 1.0 TYP Thermal Balls PCB Substrate ∅ 0. ∅ 0. Logo View ® PPC405GP 1YWWBZZZZZ CCCCCCC Lot Number C 0. 0.25 0.35 C Mold Compound ± 0.5 0.1 2.65 max 15 ...
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... SOLDERBALL x 456 16 Part Number 30.0 Typ A 35.0 31.75 1.27 PCB Substrate 2.65 max ∅ 0. ∅ 0. Revision 2.03 – September 7, 2007 Data Sheet Logo View ® PPC405GP 1YWWBZZZZZ CCCCCCC Lot Number C 0. 0.25 0.35 C Mold Compound ± 0.6 0.1 AMCC ...
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... Data Sheet Pin Lists The PPC405GP embedded controller is available as a 456-ball or a 413-ball E-PBGA. The 456-ball package is available in two sizes—35 millimeters and 27 millimeters. The 413-ball package size is 25 millimeters. In this section there are three tables that correlate the external signals to the physical package pin (ball) on which they appear ...
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Power PC 405GP Embedded Processor Signals Listed Alphabetically Signal Name 413-Ball 456-Ball EMCTxEn J21 EMCTxErr K20 EOT0/TC0 C2 EOT1/TC1 G4 EOT2/TC2 U3 EOT3/TC3 V3 ExtAck U4 ExtReq V4 ExtReset A18 A23 C14 D14 F1 F23 ...
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Revision 2.03 – September 7, 2007 Data Sheet Signals Listed Alphabetically Signal Name 413-Ball 456-Ball GND Gnt[PCIReq0] D15 GPIO1[TS1E] A20 GPIO2[TS2E] C19 GPIO3[TS1O] A21 GPIO4[TS2O] AB18 GPIO5[TS3] AC4 GPIO6[TS4] AB4 GPIO7[TS5] AC3 GPIO8[TS6] Y6 GPIO9[TrcClk] T7 [GPIO10]PerCS1 H11 [GPIO11]PerCS2 G8 ...
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Power PC 405GP Embedded Processor Signals Listed Alphabetically Signal Name 413-Ball 456-Ball MemAddr0 AA21 MemAddr1 AC22 MemAddr2 AA20 MemAddr3 AB21 MemAddr4 AA19 MemAddr5 AB20 MemAddr6 AC21 MemAddr7 Y16 MemAddr8 Y15 MemAddr9 AB19 MemAddr10 AC20 MemAddr11 AA16 MemAddr12 AA15 ...
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Revision 2.03 – September 7, 2007 Data Sheet Signals Listed Alphabetically Signal Name 413-Ball 456-Ball A11 D11 G10 G15 H9 H10 H14 H15 J7 J8 J10 J14 J16 J17 K16 L23 P16 P20 ...
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Power PC 405GP Embedded Processor Signals Listed Alphabetically Signal Name 413-Ball 456-Ball PCIAD0 B17 PCIAD1 B15 PCIAD2 B16 PCIAD3 B18 PCIAD4 A19 PCIAD5 C15 PCIAD6 C17 PCIAD7 C18 PCIAD8 C20 PCIAD9 D19 PCIAD10 A22 B22 PCIAD11 PCIAD12 D20 ...
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Revision 2.03 – September 7, 2007 Data Sheet Signals Listed Alphabetically Signal Name 413-Ball 456-Ball PerAddr0 G7 PerAddr1 J12 PerAddr2 C11 PerAddr3 C3 PerAddr4 A2 PerAddr5 C4 PerAddr6 B3 PerAddr7 D6 PerAddr8 C5 PerAddr9 B4 PerAddr10 D7 PerAddr11 A3 PerAddr12 ...
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Power PC 405GP Embedded Processor Signals Listed Alphabetically Signal Name 413-Ball 456-Ball PerData0 R3 PerData1 W1 PerData2 U2 PerData3 T2 PerData4 U1 PerData5 P2 PerData6 N2 PerData7 M3 PerData8 R1 PerData9 M2 PerData10 P1 M1 PerData11 PerData12 K1 ...
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Revision 2.03 – September 7, 2007 Data Sheet Signals Listed Alphabetically Signal Name 413-Ball 456-Ball B19 C16 D18 E2 H3 T21 V20 V21 W22 Reserved 1 Y5 AA8 AB5 SysClk H16 SysErr P14 SysReset J15 TCK U16 TDI U13 TDO ...
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Power PC 405GP Embedded Processor Signals Listed Alphabetically Signal Name 413-Ball 456-Ball A13 D12 D13 K9 K15 L9 L10 L14 L15 L20 M10 M14 N10 N14 N15 P9 P15 Y11 Y12 AC11 AB16 WE ...
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Revision 2.03 – September 7, 2007 Data Sheet Signals Listed by Ball Assignment—413-Ball Package Ball Signal Name Ball A1 GND B17 A2 PerAddr4 B18 A3 PerAddr11 B19 A4 PerAddr15 B20 A5 PerAddr18 B21 A6 GND B22 A7 PerAddr21 B23 A8 ...
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Power PC 405GP Embedded Processor Signals Listed by Ball Assignment—413-Ball Package Ball Signal Name Ball J23 PCIAD21 M2 K1 PerData12 M3 K2 PerData17 M10 ...
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Revision 2.03 – September 7, 2007 Data Sheet Signals Listed by Ball Assignment—413-Ball Package Ball Signal Name Ball W20 MemClkOut0 AA1 W21 IRQ4[GPIO21] AA2 W22 Reserved AA3 W23 PCIGnt0[Req] AA4 Y1 MemData30 AA5 Y2 MemData25 AA6 Y3 MemData23 AA7 Y4 ...
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Power PC 405GP Embedded Processor Signals Listed by Ball Assignment—456-Ball Package Ball Signal Name Ball A1 GND B14 A2 GND B15 A3 PerAddr1 B16 A4 PerCS3[GPIO12] B17 A5 PerAddr8 B18 A6 GND B19 A7 DMAReq3 B20 A8 PerAddr15 ...
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Revision 2.03 – September 7, 2007 Data Sheet Signals Listed by Ball Assignment—456-Ball Package Ball Signal Name Ball J1 PerData23 M5 J2 PerData26 M11 J3 PerData25 M12 J4 PerData27 M13 J5 GND M14 J22 GND M15 J23 PCIIRDY M16 J24 ...
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Power PC 405GP Embedded Processor Signals Listed by Ball Assignment—456-Ball Package Ball Signal Name Ball AA25 PHYCol AC8 AA26 GND AC9 AB1 MemData24 AC10 AB2 MemData21 AC11 AB3 GPIO9[TrcClk] AC12 AB4 UART0_CTS AC13 AB5 GND AC14 OV AB6 ...
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... PPC405GP has control of the external bus. When, during the course of normal chip operation, an external master gains ownership of the external bus, these same pins are used as inputs which are driven by the external master and received by the EBC in the PPC405GP. In this example, the pins are also bidirectional, serving as both inputs and outputs. ...
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... When the PCI bridge is unused, configure the PCI controller to park on the bus and actively drive PCIAD31:0, PCIC3:0[BE3:0], and the remaining PCI control signals by doing the following: - Strap the PPC405GP to disable the internal PCI arbiter and to operate the PCI interface in synchronous mode. ...
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Revision 2.03 – September 7, 2007 Data Sheet Signal Functional Description Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and ...
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Power PC 405GP Embedded Processor Signal Functional Description Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down ...
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... MemClkOut0:1 SDRAM attach without requiring this signal to be repowered by a PLL or zero-delay buffer. External Slave Peripheral Interface Peripheral data bus used by PPC405GP when not in external master mode, otherwise used by external master. PerData0:31 Note: PerData0 is the most significant bit (msb) on this bus. ...
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... When the PPC405GP is the bus master, it enables the selected device to drive the bus. Used by the PPC405GP when not in external master mode, as output by either the peripheral controller or DMA controller depending upon the type of transfer involved. High indicates a read from memory, low PerR/W indicates a write to memory ...
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... HoldPri master tenure. Used when the PPC405GP needs to regain control of peripheral BusReq interface from an external master. An input used to indicate to the PPC405GP that an external slave PerErr peripheral error occurred. Internal Peripheral Interface Serial Clock used to provide an alternate clock to the internally generated serial clock. Used in cases where the allowable internally UARTSerClk generated baud rates are not satisfactory ...
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... JTAG test clock. The frequency of this input can range from DC to TCK 25MHz. JTAG reset. TRST must be low at power-on to initialize the JTAG TRST controller and for normal operation of the PPC405GP. System Interface SysClk Main system clock input. Main system reset. External logic can drive this bidirectional pin low (minimum of 16 cycles) to initiate a system reset ...
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Revision 2.03 – September 7, 2007 Data Sheet Signal Functional Description Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and ...
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Power PC 405GP Embedded Processor Signal Functional Description Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down ...
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... Notes: 4. All specified voltages are with respect to GND. Package Thermal Specifications The PPC405GP is designed to operate within a case temperature range of -40°C to +85°C. Thermal resistance values for the E-PBGA packages (leaded and lead-free convection environment are as follows: Package—Thermal Resistance 35mm, 456-balls— ...
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Power PC 405GP Embedded Processor Recommended DC Operating Conditions Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability. Notes: 1. PCI drivers meet PCI specifications. 2. See “5V-Tolerant ...
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Revision 2.03 – September 7, 2007 Data Sheet 5V-Tolerant Input Current 100 0 -100 -200 -300 -400 -500 -600 -700 0.0 1.0 Input Capacitance Parameter 3.3V LVTTL I/O 5V tolerant LVTTL I/O PCI I/O Rx only pins AMCC 405GP – ...
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Power PC 405GP Embedded Processor DC Electrical Characteristics Parameter Active Operating Current (V )–133MHz DD Active Operating Current (V )–200MHz DD Active Operating Current (V )–266 MHz DD Active Operating Current (OV )–133MHz DD Active Operating Current (OV ...
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Revision 2.03 – September 7, 2007 Data Sheet Clocking Specifications Symbol Parameter CPU PF Processor clock frequency C PT Processor clock period C SysClk Input SCF Clock input frequency C SCT Clock period C SCT Clock edge stability (phase jitter, ...
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... Ethernet operation is unaffected. 4. IIC operation is unaffected. Caution the system designer to ensure that any SSCG used with the PPC405GP meets the above requirements and does not adversely affect other aspects of the system. 48 Revision 2.03 – ...
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Revision 2.03 – September 7, 2007 Data Sheet Peripheral Interface Clock Timings Parameter PCIClk input frequency (asynchronous mode) PCIClk period (asynchronous mode) PCI Clock frequency (synchronous mode) PCI Clock period (synchronous mode - Note 2) PCIClk input high time PCIClk ...
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Power PC 405GP Embedded Processor Input Setup and Hold Waveform Clock Inputs Output Delay and Float Timing Waveform Clock T max OV T min Outputs OH High (Drive) Float (High-Z) Low (Drive min T min IS ...
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Revision 2.03 – September 7, 2007 Data Sheet Notes all of the following I/O Specifications tables a timing values of “na” means “not applicable” and “dc” means “don’t care.” 2. See “Test Conditions” on page 46 for output ...
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Power PC 405GP Embedded Processor I/O Specifications—All speeds Notes: 1. PCI timings are for operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz. In synchronous mode, timing is relative to ...
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... SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load. 3. SDRAM interface hold times are guaranteed at the PPC405GP package pin. System designers must use the PPC405GP IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring ...
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... SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load. 3. SDRAM interface hold times are guaranteed at the PPC405GP package pin. System designers must use the PPC405GP IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring ...
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... When the SysReset input is driven low by an external device (system reset), the state of certain I/O pins is read to enable default initial conditions prior to PPC405GP start-up. The actual capture instant is the nearest SysClk edge before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0) resistors to select the desired default conditions. The recommended pull-up is 3kΩ ...
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... The tune bits adjust parameters that control PLL jitter. The recommended values minimize jitter for the PLL implemented in the PPC405GP. These bits are shown for information only; and do not require modification except in special clocking circumstances such as spread spectrum clocking. For details on the use of Spread Spectrum Clock Generators (SSCGs) with the PPC405GP, visit the technical documents area of the AMCC PowerPC web site. 2. Not all combinations of dividers produce valid operating configurations. Frequencies must be within the limits specified in “ ...
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Revision 2.03 – September 7, 2007 Data Sheet Revision Log Date 02/12/2003 Timing diagram update 04/14/2003 Update legal statements regarding document status. 06/19/2003 Add 133 MHz part numbers. 12/02/2004 Update to AMCC format. Add lead-free PNs. 01/06/2005 Correct typographical error ...
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Power PC 405GP Embedded Processor Printed in the United States of America, September 2007 The following are trademarks of AMCC in the United States, or other countries, or both: AMCC Other company, product, and service names may be ...
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... Phone: (408) 542-8600 — (800) 840-6055 — Fax: (408) 542-8601 AMCC reserves the right to make changes to its products, its datasheets, or related documentation, without notice and war- rants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available datasheet. Please consult AMCC’ ...