EVAL-ADN2814EB Analog Devices Inc, EVAL-ADN2814EB Datasheet
EVAL-ADN2814EB
Specifications of EVAL-ADN2814EB
EVAL-ADN2814EB Summary of contents
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FEATURES Serial data input: 10 Mb/s to 675 Mb/s Exceeds SONET requirements for jitter transfer/ generation/tolerance Quantizer sensitivity: 3.3 mV typical Adjustable slice level: ±95 mV Patented clock recovery architecture Loss-of-signal (LOS) detect range: 2 Independent ...
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ADN2814 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Jitter Specifications ....................................................................... 4 Output and Timing Specifications ............................................. 5 Absolute Maximum Ratings ............................................................ ...
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SPECIFICATIONS VCC = VEE = MIN MAX MIN MAX unless otherwise noted. Table 1. Parameter QUANTIZER—DC CHARACTERISTICS Input Voltage Range Peak-to-Peak Differential Input Input Common-Mode Level ...
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ADN2814 Parameter POWER SUPPLY VOLTAGE POWER SUPPLY CURRENT OPERATING TEMPERATURE RANGE 1 PIN and NIN should be differentially driven and ac-coupled for optimum sensitivity. 2 When ac-coupled, the LOS assert and deassert times are dominated by the RC time constant ...
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OUTPUT AND TIMING SPECIFICATIONS Table 3. Parameter LVDS OUTPUT CHARACTERISTICS (CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN) Output Voltage High Output Voltage Low Differential Output Swing Output Offset Voltage Output Impedance LVDS Outputs Timing Rise Time Fall Time Setup Time Hold Time ...
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ADN2814 ABSOLUTE MAXIMUM RATINGS VCC = VEE = MIN MAX MIN MAX SLICEP = SLICEN = VEE, unless otherwise noted. Table 4. Parameter Supply Voltage (VCC) ...
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TIMING CHARACTERISTICS CLKOUTP DATAOUTP/ DATAOUTN Figure 2. Output Timing DIFFERENTIAL CLKOUTP/N, DATAOUTP Figure 3. Differential Output Specifications 5mA R V LOAD DIFF 100Ω 100Ω 5mA SIMPLIFIED LVDS ...
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ADN2814 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 5. Pin Function Descriptions Pin No. Mnemonic 1 TEST1 2 VCC 3 VREF 4 NIN 5 PIN 6 SLICEP 7 SLICEN 8 VEE 9 THRADJ 10 REFCLKP 11 REFCLKN 12 VCC 13 VEE ...
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TYPICAL PERFORMANCE CHARACTERISTICS 100 1k R (Ω) TH Figure 6. LOS Comparator Trip Point Programming 10k 100k Rev Page ADN2814 ...
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ADN2814 INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION 1 MSB = 1 S SLAVE ADDR, LSB = 0 (WR) A(S) S SLAVE ADDR, LSB = 0 (WR) A( START BIT A(S) = ACKNOWLEDGE BY SLAVE START ...
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Table 6. Internal Register Map Reg Name R/W Addr D7 D6 FREQ0 R 0x0 MSB FREQ1 R 0x1 MSB FREQ2 R 0x2 0 MSB RATE R 0x3 COARSE_RD[8] MSB MISC R 0x4 x x CTRLA W 0x8 F Range ...
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ADN2814 TERMINOLOGY Input Sensitivity and Input Overdrive Sensitivity and overdrive specifications for the quantizer involve offset voltage, gain, and noise. The relationship between the logic output of the quantizer and the analog voltage input is shown in Figure 12. For ...
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JITTER SPECIFICATIONS The ADN2814 CDR is designed to achieve the best bit- error-rate (BER) performance and to exceed the jitter transfer, generation, and tolerance specifications proposed for SONET/SDH equipment defined in the Telcordia Technologies specification. Jitter is the dynamic displacement ...
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ADN2814 THEORY OF OPERATION The ADN2814 is a delay- and phase-locked loop circuit for clock recovery and data retiming from an NRZ encoded data stream. The phase of the input data signal is tracked by two separate feedback loops, which ...
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At medium jitter frequencies, the gain and tuning range of the VCO are not large enough to track input jitter. In this case, the VCO control voltage becomes large and saturates, and the VCO frequency dwells at one extreme of ...
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ADN2814 FUNCTIONAL DESCRIPTION FREQUENCY ACQUISITION The ADN2814 acquires frequency from the data over a range of data frequencies from 10 Mb/s to 675 Mb/s. The lock detector circuit compares the frequency of the VCO and the frequency of the incoming ...
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LOCK DETECTOR OPERATION The lock detector on the ADN2814 has three modes of operation: normal mode, REFCLK mode, and static LOL mode. Normal Mode In normal mode, the ADN2814 is a continuous rate CDR that locks onto any data rate ...
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ADN2814 The time to detect lock to harmonic × (T /ρ) d where: 1/T is the new data rate. For example, if the data rate is d switched from OC-12 to OC-3, then T d ρ is ...
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TTL input, providing maximum system flexibility. Phase noise and duty cycle of the reference clock are not critical, and 100 ppm accuracy is sufficient. ADN2814 REFCLKP 10 BUFFER 11 REFCLKN 100kΩ 100kΩ Figure 21. Differential REFCLK Configuration VCC ADN2814 ...
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ADN2814 ADN2814 data rate measurement. For example 100 ppm accuracy reference clock is used, the total accuracy of the measurement is within 200 ppm. The reference clock can range from 10 MHz and 160 MHz. The ADN2814 expects ...
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APPLICATIONS INFORMATION PCB DESIGN GUIDELINES Proper RF PCB design techniques must be used for optimal performance. Power Supply Connections and Ground Planes Use of one low impedance ground plane is recommended. The VEE pins should be soldered directly to the ...
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ADN2814 Transmission Lines Use of 50 Ω transmission lines is required for all high frequency input and output signals to minimize reflections: PIN, NIN, CLKOUTP, CLKOUTN, DATAOUTP, and DATAOUTN (also REFCLKP and REFCLKN high frequency reference clock is ...
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VCC C V1 TIA C V1b 1 V1 V1b V2 V2b V DIFF V = V2–V2b DIFF VTH = ADN2813 QUANTIZER THRESHOLD NOTES: 1. DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS ZERO. ...
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ADN2814 COARSE DATA RATE READBACK LOOK-UP TABLE Code is the 9-bit value read back from COARSE_RD[8:0]. Table 13. Look-Up Table Code F Code MID 0 5.3745e+ 5.3741e+ 5.4793e+ 5.5912e+ 5.7111e+ ...
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Code F Code MID 188 3.2587e+08 199 189 3.3712e+08 200 190 3.4936e+08 201 191 3.6263e+08 202 192 3.4397e+08 203 193 3.4394e+08 204 194 3.5067e+08 205 195 3.5783e+08 206 196 3.6551e+08 207 197 3.7370e+08 208 198 3.8247e+08 209 F Code F ...
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... SEATING PLANE ORDERING GUIDE Model Temperature Range 1 ADN2814ACPZ −40°C to 85°C ADN2814ACPZ-500RL7 1 −40°C to 85°C 1 ADN2814ACPZ-RL7 −40°C to 85°C 1 EVAL-ADN2814EBZ RoHS Compliant Part. 5.00 BSC SQ 0.60 MAX 24 0.50 BSC TOP 4.75 VIEW BSC SQ 0.50 0.40 17 0.30 ...
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NOTES Rev Page ADN2814 ...
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ADN2814 NOTES 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Patent Rights to use these components © ...