EVAL-ADN2814EB Analog Devices Inc, EVAL-ADN2814EB Datasheet - Page 19

• Manufacturer Part Number: EVAL-ADN2814EB
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADN2814EB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

voltage TTL input, providing maximum system flexibility. Phase
noise and duty cycle of the reference clock are not critical, and
100 ppm accuracy is sufficient.
The two uses of the reference clock are mutually exclusive. The
reference clock can be used either as an acquisition aid for the
ADN2814 to lock onto data, or to measure the frequency of the
incoming data to within 0.01%. (There is the capability to
measure the data rate to approximately ±10% without the use of
a reference clock.) The modes are mutually exclusive because, in
the first use, the user knows exactly what the data rate is and
wants to force the part to lock onto only that data rate; in the
second use, the user does not know what the data rate is and
wants to measure it.
Lock-to-reference mode is enabled by writing a 1 to I
Register Bit CTRLA[0]. Fine data rate readback mode is
enabled by writing a 1 to I
1 to both of these bits at the same time causes an indeterminate
state and is not supported.
VCC
OSC
CLK
NC
VCC
Figure 22. Single-Ended REFCLK Configuration
OUT
REFCLKN
REFCLKP
REFCLKN
Figure 21. Differential REFCLK Configuration
REFCLKP
REFCLKP
REFCLKN
Figure 23. No REFCLK Configuration
10
11
10
11
ADN2814
ADN2814
2
C Register Bit CTRLA[1]. Writing a
100kΩ
ADN2814
100kΩ
100kΩ
100kΩ
100kΩ
BUFFER
BUFFER
100kΩ
BUFFER
VCC/2
VCC/2
VCC/2
2
C
Rev. A | Page 19 of 28
Using the Reference Clock to Lock onto Data
In this mode, the ADN2814 locks onto a frequency derived
from the reference clock according to
The user must know exactly what the data rate is and provide a
reference clock that is a function of this rate. The ADN2814 can
still be used as a continuous rate device in this configuration,
provided that the user has the ability to provide a reference
clock that has a variable frequency (see Application Note
AN-632).
The reference clock can be anywhere between 10 MHz and
160 MHz. By default, the ADN2814 expects a reference clock of
between 10 MHz and 20 MHz. If it is between 20 MHz and
40 MHz, 40 MHz and 80 MHz, or 80 MHz and 160 MHz, the
user needs to configure the ADN2814 to use the correct
reference frequency range by setting two bits of the CTRLA
register, CTRLA[7:6].
Table 11. CTRLA Settings
CTRLA[7:6]
00
01
10
11
The user can specify a fixed integer multiple of the reference
clock to lock onto using CTRLA[5:2], where CTRLA should be
set to the data rate/DIV_F
divided-down reference referred to the 10 MHz to 20 MHz
band. For example, if the reference clock frequency is 38.88 MHz
and the input data rate is 622.08 Mb/s, CTRLA[7:6] is set to
[01] to give a divided-down reference clock of 19.44 MHz.
CTRLA[5:2] would be set to [0101], that is, 5, because
In this mode, if the ADN2814 loses lock for any reason, it relocks
onto the reference clock and continues to output a stable clock.
While the ADN2814 is operating in lock-to-reference mode, if
the user ever changes the reference frequency, the F
(CTRLA[7:6]), or the F
followed by writing a 0 to 1 transition into the CTRLA[0] bit to
initiate a new lock-to-reference command.
Using the Reference Clock to Measure Data Frequency
The user can also provide a reference clock to measure the
recovered data frequency. In this case, the user provides a
reference clock, and the ADN2814 compares the frequency of
the incoming data to the incoming reference clock and returns a
ratio of the two frequencies to 0.01% (100 ppm). The accuracy
error of the reference clock is added to the accuracy of the
Data Rate/2
622.08 Mb/s/19.44 MHz = 2
Range (MHz)
10 to 20
20 to 40
40 to 80
80 to 160
CTRLA[5:2]
REF
= REFCLK/2
REF
ratio (CTRLA[5:2]), this must be
, where DIV_F
5
CTRLA[5:2]
0000
0001
n
1000
CTRLA[7:6]
REF
represents the
ADN2814
REF
Ratio
1
2
2
256
range
n