CLC5526PCASM/NOPB National Semiconductor, CLC5526PCASM/NOPB Datasheet

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CLC5526PCASM/NOPB

Manufacturer Part Number
CLC5526PCASM/NOPB
Description
Manufacturer
National Semiconductor
Datasheet
1.CLC5526PCASMNOPB.pdf (11 pages)

Specifications of CLC5526PCASM/NOPB

Lead Free Status / Rohs Status
Compliant
© 2002 National Semiconductor Corporation
CLC5526
Digital Variable Gain Amplifier (DVGA)
General Description
The CLC5526 is a high performance, digitally controlled,
variable-gain amplifier (DVGA). It has been designed for use
in a broad range of mixed signal and digital communication
applications such as mobile radio, cellular base stations and
back-channel modems where automatic-gain-control (AGC)
is required to increase system dynamic range.
The CLC5526 has differential input and output, allowing
large signal swings on a single 5V rail. The input impedance
is 200Ω. The differential output impedance is 600Ω and is
designed to drive a 1 kΩ differential load. The output ampli-
fier has excellent intermodulation performance. The
CLC5526 is designed to accept signals from RF elements
and maintain a terminated impedance environment.
The CLC5526 maintains a 350 MHz bandwidth over its
entire gain and attenuation range from +30 dB to −12 dB.
Internal clamping ensures very fast overdrive recovery. Two
tone intermodulation distortion is excellent: at 150 MHz, 1
V
Input signals to the CLC5526 are scaled by an accurate,
differential R-2R resistive ladder with an input impedance of
200Ω. A scaled version of the input is selected under digital
control and passed to the internal amplifier. The input com-
mon mode level is set at 2.4V via a bandgap referenced bias
generator which can be overridden by an external input.
Following the resistive ladder is a fixed, 30 dB gain amplifier.
The output stage common mode voltage of the CLC5526 is
set to 3V, by internal, positive supply connected resistors.
Digital control of the CLC5526 is accomplished by a 3-bit
parallel gain control input and a data valid pin to latch the
data. If the data is not latched, the DVGA is transparent to
gain control updates. All digital inputs are TTL/CMOS com-
patible.
A shutdown input reduces the CLC5526 supply currrent to a
few mA. During shutdown, the input termination is main-
tained and current attenuation settings are held.
pp
it is −64 dBc.
DS015016
The CLC5526 operates over the industrial temperature
range of −40˚C to +85˚C. The part is available in a 20-pin
SSOP package.
Features
n 350 MHz bandwidth
n Differential input and output
n Gain control: parallel w/data latching
n Supply voltage: +5V
n Supply current: 48 mA
Key Specifications
n Low two tone intermod:
n Low noise: 2.5 nV/
n Wide gain range: +30 dB to −12 dB
n Gain step size: 6 dB
Applications
n Cellular/PCS base stations
n IF sampling receivers
n Infrared/CCD imaging
n Back-channel modems
n Electro-optics
n Instrumentation
n Medical imaging
n High definition video
9.3 dB noise figure (max gain)
distortion: −64 dBc
24.5 dBm IP3, 150 MHz
√
Hz (max gain),
@
1 V
PP
, 150 MHz
September 2002
www.national.com

CLC5526PCASM/NOPB Summary of contents

Page 1

... A shutdown input reduces the CLC5526 supply currrent to a few mA. During shutdown, the input termination is main- tained and current attenuation settings are held. © 2002 National Semiconductor Corporation The CLC5526 operates over the industrial temperature range of −40˚C to +85˚C. The part is available in a 20-pin SSOP package ...

Page 2

Block Diagram Pin Configuration Pin Pin Name No. GND 10, 11, 13, 20 Gain MSB Gain ISB Gain LSB In+ In− Ref Comp V 16 Shutdown Latch Data Out+ Out− Ref In www.national.com Ordering Information ...

Page 3

... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Positive Supply Voltage ( Differential Voltage between any Two Grounds Analog Input Voltage Range Digital Input Voltage Range Output Short Circuit Duration ...

Page 4

Electrical Characteristics The following specifications apply for V −40˚ +85˚C, all other limits T max Symbol Parameter Maximum Gain Minimum Gain Gain Step Size Gain Step Accuracy Cumulative Gain Step Error DIGITAL INPUTS/TIMING Logic Compatibility V Logic ...

Page 5

Typical Performance Characteristics Gain vs. Frequency 2nd and 3rd Harmonic Distortion vs. Frequency Distortion vs. Gain Setting (V = +5V kΩ, max gain; unless specified Transconductance vs. Frequency 01501603 2-Tone, 3rd Order Intermodulation Output Intercept ...

Page 6

Typical Performance Characteristics (Continued) 6dB Gain Step, Time Domain Response Input Referred Thermal Noise vs. Gain Setting (Gain Block) Differential Z vs. Frequency IN www.national.com (V = +5V kΩ, max gain; unless specified Gain Step ...

Page 7

Timing Diagram Truth Table Gain Word MSB 01501615 ISB LSB ...

Page 8

Applications DESCRIPTION The CLC5526 is a digitally programmable, variable gain amplifier with the following features: • 8 gain settings ranging from − 6dB steps • Differential inputs and outputs (externally AC coupled) • Self biased input ...

Page 9

... FIGURE 5. Diversity Receiver Chipset Layout Considerations 01501619 A proper printed circuit layout is essential for achieving high frequency performance. National Semiconductor provides evaluation boards for the CLC5526, which include input and output transformers for impedance matching and single to differential signal conversion. Supply bypassing is required for best performance. Provide a 6.8 µ ...

Page 10

Evaluation Board Layout and Schematic Diagram CLC5526 Layer 1 www.national.com 01501622 CLC5526 Layer 2 Evaluation Board Schematic 10 01501623 01501624 ...

Page 11

... NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant ...