ADC12V170LFEB National Semiconductor, ADC12V170LFEB Datasheet - Page 16

• Manufacturer Part Number: ADC12V170LFEB
• Manufacturer: National Semiconductor

Specifications of ADC12V170LFEB

• Lead Free Status / Rohs Status: Compliant

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Functional Description
Operating on dual +3.3V and +1.8V supplies, the AD-
C12V170 digitizes a differential analog input signal to 12 bits,
using a differential pipelined architecture with error correction
circuitry and an on-chip sample-and-hold circuit to ensure
maximum performance.
The user has the choice of using an internal 1.0V stable ref-
erence, or using an external reference. The ADC12V170 will
accept an external reference between 0.9V and 1.1V (1.0V
recommended) which is buffered on-chip to ease the task of
driving that pin. The +1.8V output driver supply reduces pow-
er consumption and decreases the noise at the output of the
converter.
The quad state function pin CLK_SEL/DF (pin 8) allows the
user to choose between using a single-ended or a differential
clock input and between offset binary or 2's complement out-
put data format. The digital outputs are LVDS compatible
signals that are clocked by a synchronous data ready output
signal (DRDY pins 33, 34) at the same rate as the clock input.
For the ADC12V170 the clock frequency can be between 5
MSPS and 170 MSPS (typical) with fully specified perfor-
mance at 170 MSPS. The analog input is acquired at the
falling edge of the clock and the digital data for a given sample
is output on the falling edge of the DRDY signal and is delayed
by the pipeline for 7.5 clock cycles. The odd data bits should
be captured with the rising edge of DRDY and the even data
bits should be captured with the falling edge of DRDY.
Power-down is selectable using the PD/Sleep pin (pin 7). A
logic high on the PD/Sleep pin disables everything except the
voltage reference circuitry and reduces the converter power
consumption to 15 mW. When PD/Sleep is biased to V
the chip enters sleep mode. In sleep mode everything except
the voltage reference circuitry and its accompanying on chip
buffer is disabled; power consumption is reduced to 50 mW.
The ADC12V170's wake-up time is quicker from sleep mode
than from power down mode. For normal operation, the PD/
Sleep pin should be connected to the analog ground (AGND).
A duty cycle stabilizer maintains performance over a wide
range of clock duty cycles.
Applications Information
1.0 OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC12V170:
3.0V
V
V
5 MHz
1.0V internal reference
0.9V
V
Single Ended Clock Mode
D
DR
CM
= V
= 1.8V
= 1.5V (from V
≤
≤
A
≤
V
V
A
REF
f
CLK
≤
3.6V
≤
≤
1.1V (for an external reference)
170 MHz
RM
)
A
/2 the
16
2.0 ANALOG INPUTS
2.1 Signal Inputs
2.1.1 Differential Analog Input Pins
The ADC12V170 has one pair of analog signal input pins,
V
signal, V
Figure 2 shows the expected input signal range. Note that the
common mode input voltage, V
V
mode level for the analog input signal. The peaks of the indi-
vidual input signals should each never exceed 2.6V. Each
analog input pin of the differential pair should have a peak-to-
peak voltage equal to the reference voltage, V
out of phase with each other and be centered around
V
should not exceed the value of the reference voltage or the
output data will be clipped.
For single frequency sine waves the full scale error in LSB
can be described as approximately
Where dev is the angular difference in degrees between the
two signals having a 180° relative phase relationship to each
other (see Figure 3). For single frequency inputs, angular er-
rors result in a reduction of the effective full scale input. For
complex waveforms, however, angular errors will result in
distortion.
FIGURE 3. Angular Errors Between the Two Input Signals
It is recommended to drive the analog inputs with a source
impedance less than 100Ω. Matching the source impedance
for the differential inputs will improve even ordered harmonic
performance (particularly second harmonic).
Table 1 indicates the input to output relationship of the
ADC12V170.
IN
RM
CM
+ and V
Will Reduce the Output Level or Cause Distortion
.The peak-to-peak voltage swing at each analog input pin
(pin 45) for V
IN
FIGURE 2. Expected Input Signal Range
, is defined as
IN
−, which form a differential input pair. The input
E
FS
= 4096 ( 1 - sin (90° + dev))
CM
V
IN
will ensure the proper input common
= (V
IN
+) – (V
CM
, should be 1.5V. Using
IN
−)
30016816
30016814
REF
, be 180°