ADC12V170LFEB National Semiconductor, ADC12V170LFEB Datasheet - Page 19

• Manufacturer Part Number: ADC12V170LFEB
• Manufacturer: National Semiconductor

Specifications of ADC12V170LFEB

• Lead Free Status / Rohs Status: Compliant

4.0 DIGITAL OUTPUTS
Digital outputs consist of the LVDS signals D0-D11, DL,
DRDY and OVR.
The ADC12V170 has 16 LVDS compatible data output pins:
12 data output bits corresponding to the converted input val-
ue, 2 output pins that are always set to LVDS low, a data ready
(DRDY) signal that should be used to capture the output data
and an over-range indicator (OVR) which is set high when the
sample amplitude exceeds the 12-Bit conversion range. Valid
data is present at these outputs while the PD/Sleep pin is low.
The odd data bits should be captured with the falling edge of
DRDY and the even data bits should be captured with the
rising edge of DRDY.
Be very careful when driving a high capacitance bus. The
more capacitance the output drivers must charge for each
conversion, the more instantaneous digital current flows
19
through V
spikes can cause on-chip ground noise and couple into the
analog circuitry, degrading dynamic performance. Adequate
bypassing, limiting output capacitance and careful attention
to the ground plane will reduce this problem. Additionally, bus
capacitance beyond the specified 5 pF/pin will cause t
increase, reducing the setup and hold time of the ADC output
data. The result could be an apparent reduction in dynamic
performance.
To minimize noise due to output switching, the load currents
at the digital outputs should be minimized. This can be
achieved by keeping the PCB traces less than 2 inches long;
longer traces are more susceptible to noise. Try to place the
100 ohm termination resistor as close to the receiving circuit
as possible. See Figure 4.
DR
and DRGND. These large charging current
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OD
to