PIC32MX340F128LT-80V/BG Microchip Technology, PIC32MX340F128LT-80V/BG Datasheet - Page 141

• Manufacturer Part Number: PIC32MX340F128LT-80V/BG
• Description: 128 KB Flash, 32 KB RAM, 80 MHz, 10-Bit ADC, DMA 121 XBGA 10x10x1.20mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX340F128LT-80V/BG

• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 32 KB
• Interface Type: USB, I2C, UART, RS-232, RS-485, SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 5
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: XBGA-121
• Operating Temperature Range: - 40 C to + 105 C
• Supply Current (max): 10 mA
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: -
• Eeprom Size: -
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

27.0
The PIC32MX3XX/4XX family instruction set complies
with the MIPS32 Release 2 instruction set architecture.
PIC32MX does not support the following features:
• CoreExtend instructions
• Coprocessor 1 instructions
• Coprocessor 2 instructions
TABLE 27-1:
© 2011 Microchip Technology Inc.
ADD
ADDI
ADDIU
ADDU
AND
ANDI
B
BAL
BEQ
BEQL
BGEZ
BGEZAL
BGEZALL
BGEZL
BGTZ
BGTZL
BLEZ
Note 1:
Instruction
INSTRUCTION SET
This instruction is deprecated and should not be used.
MIPS32
Integer Add
Integer Add Immediate
Unsigned Integer Add Immediate
Unsigned Integer Add
Logical AND
Logical AND Immediate
Unconditional Branch
(Assembler idiom for: BEQ r0, r0, offset)
Branch and Link
(Assembler idiom for: BGEZAL r0, offset)
Branch on Equal
Branch on Equal Likely
Branch on Greater Than or Equal to Zero
Branch on Greater Than or Equal to Zero and Link
Branch on Greater Than or Equal to Zero and Link
Likely
Branch on Greater Than or Equal to Zero Likely
Branch on Greater Than Zero
Branch on Greater Than Zero Likely
Branch on Less Than or Equal to Zero
(1)
®
INSTRUCTION SET
Description
(1)
(1)
Table 27-1
are implemented by the PIC32MX3XX/4XX family
core.
Note:
(1)
PIC32MX3XX/4XX
provides a summary of the instructions that
Rd = Rs + Rt
Rt = Rs + Immed
Rt = Rs +
Rd = Rs +
Rd = Rs & Rt
Rt = Rs & (0
PC += (int)offset
GPR[31] = PC + 8
PC += (int)offset
if Rs == Rt
if Rs == Rt
else
if !Rs[31]
GPR[31] = PC + 8
if !Rs[31]
GPR[31] = PC + 8
if !Rs[31]
else
if !Rs[31]
else
if !Rs[31] && Rs != 0
if !Rs[31] && Rs != 0
else
if Rs[31] || Rs == 0
Refer to “MIPS32
grammers Volume II: The MIPS32
Instruction Set” at
more information.
PC += (int)offset
PC += (int)offset
Ignore Next Instruction
PC += (int)offset
PC += (int)offset
PC += (int)offset
Ignore Next Instruction
PC += (int)offset
Ignore Next Instruction
PC += (int)offset
PC += (int)offset
Ignore Next Instruction
PC += (int)offset
U
U
Immed
Rt
Function
16
®
|| Immed)
Architecture for Pro-
www.mips.com
DS61143H-page 141
for
®