PIC32MX340F128LT-80V/BG Microchip Technology, PIC32MX340F128LT-80V/BG Datasheet - Page 60

• Manufacturer Part Number: PIC32MX340F128LT-80V/BG
• Description: 128 KB Flash, 32 KB RAM, 80 MHz, 10-Bit ADC, DMA 121 XBGA 10x10x1.20mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX340F128LT-80V/BG

• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 32 KB
• Interface Type: USB, I2C, UART, RS-232, RS-485, SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 5
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: XBGA-121
• Operating Temperature Range: - 40 C to + 105 C
• Supply Current (max): 10 mA
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: -
• Eeprom Size: -
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

TABLE 4-11:
Legend:
Note
6000 U1MODE
6010
6020
6030
6040
6200 U2MODE
6210
6220
6230
6240
1:
U1TXREG
U1RXREG
U2TXREG
U2RXREG
U1BRG
U2BRG
U1STA
U2STA
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See
(1)
(1)
(1)
(1)
(1)
(1)
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
UART1-2 REGISTERS MAP
31/15
ON
UTXISEL<1:0>
ON
UTXISEL<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30/14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UTXINV
UTXINV
29/13
SIDL
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
URXEN
URXEN
28/12
IREN
IREN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UTXBRK
UTXBRK
RTSMD
RTSMD
27/11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UTXEN
UTXEN
26/10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UTXBF
UTXBF
25/9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UEN<1:0>
UEN<1:0>
ADM_EN
ADM_EN
TRMT
TRMT
24/8
RX8
RX8
TX8
TX8
—
—
—
—
—
—
—
—
BRG<15:0>
BRG<15:0>
Bits
WAKE
WAKE
23/7
URXISEL<1:0>
URXISEL<1:0>
—
—
—
—
—
—
—
—
LPBACK
LPBACK
22/6
—
—
—
—
—
—
—
—
Section 12.1.1 “CLR, SET and INV Registers”
ABAUD
ADDEN
ABAUD
ADDEN
21/5
—
—
—
—
—
—
—
—
RXINV
RXINV
RIDLE
RIDLE
Transmit Register
Transmit Register
20/4
Receive Register
Receive Register
—
—
—
—
—
—
—
—
ADDR<7:0>
ADDR<7:0>
BRGH
BRGH
PERR
PERR
19/3
—
—
—
—
—
—
—
—
FERR
FERR
18/2
—
—
—
—
—
—
—
—
PDSEL<1:0>
PDSEL<1:0>
for more information.
OERR
OERR
17/1
—
—
—
—
—
—
—
—
URXDA
URXDA
STSEL
STSEL
16/0
—
—
—
—
—
—
—
—
0000
0000
0000
0110
0000
0000
0000
0000
0000
0000
0000
0000
0000
0110
0000
0000
0000
0000
0000
0000