PIC32MX675F512L-80V/PF Microchip Technology, PIC32MX675F512L-80V/PF Datasheet - Page 155
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PIC32MX675F512L-80V/PF
Manufacturer Part Number
PIC32MX675F512L-80V/PF
Description
512 KB Flash, 64 KB RAM, USB-OTG, Ethernet, 80 MHz, 10-Bit ADC, DMA 100 TQFP 14x
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.PIC32MX575F256H-80VPT.pdf
(256 pages)
Specifications of PIC32MX675F512L-80V/PF
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
Ethernet, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX675F512L-80V/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
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23.0
The Controller Area Network (CAN) module supports
the following key features:
• Standards Compliance:
FIGURE 23-1:
© 2009-2011 Microchip Technology Inc.
- Full CAN 2.0B compliance
- Programmable bit rate up to 1 Mbps
Note 1: This data sheet summarizes the features
2: Some registers and associated bits
CONTROLLER AREA
NETWORK (CAN)
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 34. “Controller
Area Network (CAN)” (DS61154) in the
“PIC32 Family Reference Manual” , which
is available from the Microchip web site
(www.microchip.com/PIC32).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
CxTX
CxRX
PIC32 CAN MODULE BLOCK DIAGRAM
Message Buffer 31
Message Buffer 1
Message Buffer 0
FIFO0
CAN Module
32 Filters
4 Masks
CAN Message FIFO (up to 32 FIFOs)
Message Buffer 31
Message Buffer 1
Message Buffer 0
System Bus
System RAM
FIFO1
in
• Message Reception and Transmission:
• Additional Features:
Figure 23-1
module.
PIC32MX5XX/6XX/7XX
- 32 message FIFOs
- Each FIFO can have up to 32 messages for a
- FIFO can be a transmit message FIFO or a
- User-defined priority levels for message
- 32 acceptance filters for message filtering
- Four acceptance filter mask registers for
- Automatic response to remote transmit request
- DeviceNet™ addressing support
- Loopback, Listen All Messages and Listen
- Low-power operating modes
- CAN module is a bus master on the PIC32
- Use of DMA is not required
- Dedicated time-stamp timer
- Dedicated DMA channels
- Data-only Message Reception mode
total of 1024 messages
receive message FIFO
FIFOs used for transmission
message filtering
Only modes for self-test, system diagnostics
and bus monitoring
system bus
Message Buffer 31
Message Buffer 1
Message Buffer 0
CPU
illustrates the general structure of the CAN
FIFO31
2 or 4 Words
Buffer Size
Message
DS61156G-page 155
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