PIC32MX675F512L-80V/PF Microchip Technology, PIC32MX675F512L-80V/PF Datasheet - Page 80
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC32MX675F512L-80V/PF
Manufacturer Part Number
PIC32MX675F512L-80V/PF
Description
512 KB Flash, 64 KB RAM, USB-OTG, Ethernet, 80 MHz, 10-Bit ADC, DMA 100 TQFP 14x
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.PIC32MX575F256H-80VPT.pdf
(256 pages)
Specifications of PIC32MX675F512L-80V/PF
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
Ethernet, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX675F512L-80V/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
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- Download datasheet (6Mb)
TABLE 4-12:
Legend:
Note
5400 I2C2CON
5410 I2C2STAT
5420
5430 I2C2MSK
5440 I2C2BRG
5450 I2C2TRN
5460 I2C2RCV
1:
I2C4DD
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
for more information.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0 ACKSTAT
15:0
15:0
15:0
15:0
15:0
I2C2 REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L,
PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L,
PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES
31/15
ON
—
—
—
—
—
—
—
—
—
—
—
—
TRSTAT
30/14
FRZ
—
—
—
—
—
—
—
—
—
—
—
—
29/13
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
SCLREL
28/12
—
—
—
—
—
—
—
—
—
—
—
—
—
STRICT
27/11
—
—
—
—
—
—
—
—
—
—
—
—
26/10
A10M
BCL
—
—
—
—
—
—
—
—
—
—
—
GCSTAT
DISSLW
25/9
—
—
—
—
—
—
—
—
—
ADD10
SMEN
24/8
—
—
—
—
—
—
—
—
—
Bits
IWCOL
GCEN
23/7
—
—
—
—
—
—
—
Baud Rate Generator Register
STREN
I2COV
22/6
—
—
—
—
—
—
—
ACKDT
21/5
D/A
—
—
—
—
—
—
—
ADD<9:0>
MSK<9:0>
ACKEN
Transmit Register
Receive Register
20/4
—
—
—
—
—
—
—
P
RCEN
19/3
—
—
—
—
—
—
—
S
(1)
Section 12.1.1 “CLR, SET and INV Registers”
18/2
PEN
R/W
—
—
—
—
—
—
—
RSEN
17/1
RBF
—
—
—
—
—
—
—
16/0
SEN
TBF
—
—
—
—
—
—
—
0000
1000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
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