PIC32MX675F512L-80V/PT Microchip Technology, PIC32MX675F512L-80V/PT Datasheet - Page 94
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PIC32MX675F512L-80V/PT
Manufacturer Part Number
PIC32MX675F512L-80V/PT
Description
512 KB Flash, 64 KB RAM, USB-OTG, Ethernet, 80 MHz, 10-Bit ADC, DMA 100 TQFP 12x
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.PIC32MX575F256H-80VPT.pdf
(256 pages)
Specifications of PIC32MX675F512L-80V/PT
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
Ethernet, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX675F512L-80V/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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TABLE 4-20:
TABLE 4-21:
Legend:
Note 1:
Legend:
Note
A000 CM1CON
A010 CM2CON
A060 CMSTAT
9800 CVRCON
1:
2:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
more information.
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
more information.
These bits are not available on PIC32MX575/675/695/775 devices. On these devices, reset value for CVRCON is 0000.
31:16
15:0
31:16
31:16
31:16
15:0
15:0
15:0
COMPARATOR REGISTER MAP
COMPARATOR VOLTAGE REFERENCE REGISTER MAP
31/15
31/15
ON
—
ON
ON
—
—
—
—
30/14
30/14
COE
COE
FRZ
—
—
—
—
—
29/13
29/13
CPOL
CPOL
SIDL
—
—
—
—
—
28/12
28/12
—
—
—
—
—
—
—
—
(1)
27/11
27/11
—
—
—
—
—
—
—
—
VREFSEL
26/10
26/10
—
—
—
—
—
—
—
(2)
25/9
—
—
—
—
—
—
25/9
BGSEL<1:0>
—
COUT
COUT
24/8
—
—
—
—
24/8
(1)
—
(2)
Bits
Bits
23/7
—
EVPOL<1:0>
—
EVPOL<1:0>
—
—
23/7
—
—
22/6
CVROE
—
—
—
—
22/6
—
21/5
CVRR
—
—
—
—
—
—
21/5
—
CREF
CREF
20/4
CVRSS
—
—
—
—
20/4
—
19/3
Section 12.1.1 “CLR, SET and INV Registers”
Section 12.1.1 “CLR, SET and INV Registers”
—
—
—
—
—
—
19/3
—
18/2
—
—
—
—
—
—
18/2
—
CVR<3:0>
C2OUT
17/1
—
—
—
17/1
CCH<1:0>
CCH<1:0>
—
C1OUT
16/0
16/0
—
—
—
—
0000
0100
0000
00C3
0000
00C3
0000
0000
for
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