STM32W108C8U63TR STMicroelectronics, STM32W108C8U63TR Datasheet - Page 30

• Manufacturer Part Number: STM32W108C8U63TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108C8U63TR

• Applications: RF4CE, Remote Control
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (64 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 24
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Radio frequency module
5.2.1
5.2.2
5.3
5.4
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Tx baseband
The STM32W108C8 Tx baseband in the digital domain spreads the 4-bit symbol into its
IEEE 802.15.4-2003-defined 32-chip sequence. It also provides the interface for software to
calibrate the Tx module to reduce silicon process, temperature, and voltage variations.
TX_ACTIVE and nTX_ACTIVE signals
For applications requiring an external PA, two signals are provided called TX_ACTIVE and
nTX_ACTIVE. These signals are the inverse of each other. They can be used for external PA
power management and RF switching logic. In transmit mode the Tx baseband drives
TX_ACTIVE high, as described in
receive mode the TX_ACTIVE signal is low. TX_ACTIVE is the alternate function of PC5,
and nTX_ACTIVE is the alternate function of PC6. See
input/outputs on page 54
Calibration
The ST RF software driver calibrates the radio using dedicated hardware resources.
Integrated MAC module
The STM32W108C8 integrates most of the IEEE 802.15.4 MAC requirements in hardware.
This allows the ARM® Cortex-M3 CPU to provide greater bandwidth to application and
network operations. In addition, the hardware acts as a first-line filter for unwanted packets.
The STM32W108C8 MAC uses a DMA interface to RAM to further reduce the overall ARM®
Cortex-M3 CPU interaction when transmitting or receiving packets.
When a packet is ready for transmission, the software configures the Tx MAC DMA by
indicating the packet buffer RAM location. The MAC waits for the backoff period, then
switches the baseband to Tx mode and performs channel assessment. When the channel is
clear the MAC reads data from the RAM buffer, calculates the CRC, and provides 4-bit
symbols to the baseband. When the final byte has been read and sent to the baseband, the
CRC remainder is read and transmitted.
The MAC is in Rx mode most of the time. In Rx mode various format and address filters
keep unwanted packets from using excessive RAM buffers, and prevent the CPU from being
unnecessarily interrupted. When the reception of a packet begins, the MAC reads 4-bit
symbols from the baseband and calculates the CRC. It then assembles the received data for
storage in a RAM buffer. Rx MAC DMA provides direct access to RAM. Once the packet has
been received additional data, which provides statistical information on the packet to the
software stack, is appended to the end of the packet in the RAM buffer space.
for details of the alternate GPIO functions.
Doc ID 018587 Rev 1
Table 10: GPIO signal assignments on page
Section 8: General-purpose
STM32W108C8
61. In