STM32W108C8U63TR STMicroelectronics, STM32W108C8U63TR Datasheet - Page 44
STM32W108C8U63TR
Manufacturer Part Number
STM32W108C8U63TR
Description
16/32-BITS MICROS
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet
1.STM32W108C8U63TR.pdf
(207 pages)
Specifications of STM32W108C8U63TR
Applications
RF4CE, Remote Control
Core Processor
ARM® Cortex-M3™
Program Memory Type
FLASH (64 kB)
Controller Series
STM32W
Ram Size
8K x 8
Interface
I²C, SPI, UART/USART
Number Of I /o
24
Voltage - Supply
1.18 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-VFQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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15
31
15
31
15
14
30
14
30
14
Bits [15:0] SLEEPTMR_CNTH_FIELD:
Bits [15:0] SLEEPTMR_CNTL_FIELD:
Bits [15:0] SLEEPTMR_CMPAH_FIELD:
Sleep timer count low register (SLEEPTMR_CNTL)
Address:
Reset value:
Sleep timer compare A high register (SLEEPTMR_CMPAH)
Address:
Reset value:
13
29
13
29
13
Sleep timer counter high value [31:16].
Reading this register updates the SLEEP_COUNT_L for subsequent reads.
Sleep timer counter low value [15:16].
This register is only valid following a read of the SLEEPTMR_CNTH register.
Sleep timer compare A high value [31:16].
Sleep timer compare value, writing updates COMP_A_H (directly) and COMP_A_L (from
hold register).
Can only be changed when the ENABLE bit (bit 11 of SLEEP_CONFIG register) is set to ‘0’.
If changed when the ENABLE bit is set to ‘1’, a spurious interrupt may be generated.
Therefore it is recommended to disable interrupts before changing this register.
12
28
12
28
12
11
27
11
27
11
0x4000 6014
0x0000 0000
0x4000 6018
0x0000 FFFF
10
26
10
26
10
25
25
9
9
9
Doc ID 018587 Rev 1
SLEEPTMR_CMPAH
SLEEPTMR_CNTH
SLEEPTMR_CNTL
24
24
8
8
8
Reserved
Reserved
rw
r
r
23
23
7
7
7
22
22
6
6
6
21
21
5
5
5
20
20
4
4
4
19
19
3
3
3
18
18
2
2
2
STM32W108C8
17
17
1
1
1
16
16
0
0
0
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