STM32W108C8U64TR STMicroelectronics, STM32W108C8U64TR Datasheet - Page 47
![no-image](/images/manufacturer_photos/0/6/637/stmicroelectronics_sml.jpg)
STM32W108C8U64TR
Manufacturer Part Number
STM32W108C8U64TR
Description
16/32-BITS MICROS
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet
1.STM32W108C8U63TR.pdf
(207 pages)
Specifications of STM32W108C8U64TR
Applications
RF4CE, Remote Control
Core Processor
ARM® Cortex-M3™
Program Memory Type
FLASH (64 kB)
Controller Series
STM32W
Ram Size
8K x 8
Interface
I²C, SPI, UART/USART
Number Of I /o
24
Voltage - Supply
1.18 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-VFQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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STM32W108C8
31
15
31
15
30
14
30
14
Sleep timer interrupt mask register (INT_SLEEPTMRCFG)
Address:
Reset value:
Sleep timer clock source enables (SLEEPTMR_CLKEN)
This timer controls the low power clock gated modes.
Clearing CLKRC_EN before executing WFE with SLEEPDEEP bit set in the NVIC System
control register causes DEEP_SLEEP2 to be entered. Setting this bit causes
DEEP_SLEEP1 to be entered.
Address:
Reset value:
Bit 2 INT_ SLEEPTMR CMPB: Sleep timer compare B
Bit 1 INT_SLEEPTMRCMPA: Sleep timer compare A
Bit 0 INT_SLEEPTMRWRAP: Sleep timer overflow
Bit 1 SLEEPTMR_CLK10KEN: Enables 10kHz internal RC during deep
Bit 0 SLEEPTMR_CLK32KEN: Enables 32kHz external XTAL
29
13
29
13
Note: Bits are cleared when set to ‘1’.
Note: Bits are cleared when set to ‘1’.
28
12
28
12
27
11
27
11
0x4000 A054
0x0000 0000
0x4000 0008
0x0000 0002
26
10
26
10
25
Reserved
9
Reserved
25
9
r
Doc ID 018587 Rev 1
r
24
8
24
8
Reserved
Reserved
23
7
23
7
22
6
22
6
21
5
21
5
20
4
20
4
19
3
19
3
18
2
SLEEP
CMPB
INT_
TMR
System modules
18
rw
2
CLK10K
SLEEP
TMR_
EN
17
rw
1
SLEEP
CMPA
INT_
TMR
17
rw
1
CLK32K
SLEEP
TMR_
47/207
SLEEP
WRAP
EN
16
rw
INT_
TMR
0
16
rw
0
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