5V49EE703NDGI8 IDT, Integrated Device Technology Inc, 5V49EE703NDGI8 Datasheet - Page 22

• Manufacturer Part Number: 5V49EE703NDGI8
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Programmable PLL Clock Synthesizerr

Specifications of 5V49EE703NDGI8

• Number Of Elements: 4
• Pll Input Freq (min): 1MHz
• Pll Input Freq (max): 200MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VFQFPN EP
• Output Frequency Range: 0.001 to 200MHz
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Pin Count: 28
• Lead Free Status / Rohs Status: Compliant

IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
Addr
0x2C
0x2D
0x3C
0x3D
0x4C
0x4D
0x28
0x29
0x2A
0x2B
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
IDT5V49EE703
EEPROM PROGRAMMABLE CLOCK GENERATOR
Register
Default
Value
Hex
00
00
00
00
00
00
01
01
01
01
01
01
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
01
01
01
01
01
01
80
80
80
80
80
80
00
00
00
00
SSENB_CFG0
SSENB_CFG1
SSENB_CFG2
SSENB_CFG3
SSENB_CFG4
SSENB_CFG5
CZ2_CFG4
CZ2_CFG5
CZ2_CFG0
CZ2_CFG1
CZ2_CFG2
CZ2_CFG3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
7
6
N3[11:8]_CFG0
N3[11:8]_CFG1
N3[11:8]_CFG2
N3[11:8]_CFG3
N3[11:8]_CFG4
N3[11:8]_CFG5
0
0
0
0
0
0
IP2[2:0]_CFG4
IP2[2:0]_CFG5
IP2[2:0]_CFG0
IP2[2:0]_CFG1
IP2[2:0]_CFG2
IP2[2:0]_CFG3
5
0
0
0
0
0
0
IP3[4]_CFG0
IP3[4]_CFG1
IP3[4]_CFG2
IP3[4]_CFG3
IP3[4]_CFG4
IP3[4]_CFG5
4
N1[7:0]_CFG4
N1[7:0]_CFG5
N1[7:0]_CFG0
N1[7:0]_CFG1
N1[7:0]_CFG2
N1[7:0]_CFG3
N2[7:0]_CFG4
N2[7:0]_CFG5
N2[7:0]_CFG0
N2[7:0]_CFG1
N2[7:0]_CFG2
N2[7:0]_CFG3
Reserved
Reserved
Reserved
Reserved
Bit #
D1[6:0]_CFG0
D1[6:0]_CFG1
D1[6:0]_CFG2
D1[6:0]_CFG3
D1[6:0]_CFG4
D1[6:0]_CFG5
D2[6:0]_CFG0
D2[6:0]_CFG1
D2[6:0]_CFG2
D2[6:0]_CFG3
D2[6:0]_CFG4
D2[6:0]_CFG5
22
3
2
N1[11:8]_CFG0
N1[11:8]_CFG1
N1[11:8]_CFG2
N1[11:8]_CFG3
N1[11:8]_CFG4
N1[11:8]_CFG5
RZ2[3:0]_CFG4
RZ2[3:0]_CFG5
RZ2[3:0]_CFG0
RZ2[3:0]_CFG1
RZ2[3:0]_CFG2
RZ2[3:0]_CFG3
N2[11:8]_CFG0
N2[11:8]_CFG1
N2[11:8]_CFG2
N2[11:8]_CFG3
N2[11:8]_CFG4
N2[11:8]_CFG5
1
0
IDT5V49EE703
CLOCK SYNTHESIZER
PLL1 input divider and input sel
D1[6:0] - 127 step Ref Div
D1 = 0 means power down.
N - Feedback Divider
2 - 4095 (value of “0” is not
allowed) Total feedback with A,
using provided calculation
PLL3 Feedback Divider
PLL2 Loop Parameter
PLL2 Reference Divide and Input
Select
D2[6:0] - 127 step Ref Div
D2 = 0 means power down.
N2[7:0] - PLL2 Feedback Divider
2 - 4095 (value of “0” is not
allowed).
(See Addr 0x4C:0x51 for
N2[15:8])
N2[11:8] - PLL2 Feedback Divide
PLL3 Spread Spectrum
SSENB - Spread Spectrum
Enable
SSENB = 1 means ON
IP3[4:0] - PLL3 Charge Pump
Current.
Description
REV F 022310