5V49EE703NDGI8 IDT, Integrated Device Technology Inc, 5V49EE703NDGI8 Datasheet - Page 25

• Manufacturer Part Number: 5V49EE703NDGI8
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Programmable PLL Clock Synthesizerr

Specifications of 5V49EE703NDGI8

• Number Of Elements: 4
• Pll Input Freq (min): 1MHz
• Pll Input Freq (max): 200MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VFQFPN EP
• Output Frequency Range: 0.001 to 200MHz
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Pin Count: 28
• Lead Free Status / Rohs Status: Compliant

Default Configuration: OUT1 = Reference Clock output, all
other outputs turned off.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
Addr
0xCC
0xCD
0xAC
0xAD
0xAE
0xAF
0xBA
0xBB
0xBC
0xBD
0xBE
0xBF
0xC0
0xC1
0xC2
0xC3
0xC4
0xC5
0xC6
0xC7
0xC8
0xC9
0xCA
0xCB
0xCE
0xCF
0xB0
0xB1
0xB2
0xB3
0xB4
0xB5
0xB6
0xB7
0xB8
0xB9
IDT5V49EE703
EEPROM PROGRAMMABLE CLOCK GENERATOR
Register
Default
Value
Hex
AE
AE
AE
AE
AE
AE
00
00
00
00
00
00
00
00
00
00
00
00
11
11
11
11
11
11
24
24
24
24
24
24
49
49
49
49
49
49
SRC4[0]_CFG0
SRC4[0]_CFG1
SRC4[0]_CFG2
SRC4[0]_CFG3
SRC4[0]_CFG4
SRC4[0]_CFG5
DITH_CFG4
DITH_CFG5
DITH_CFG0
DITH_CFG1
DITH_CFG2
DITH_CFG3
7
SRC1[1:0]_CFG4
SRC1[1:0]_CFG5
SRC1[1:0]_CFG0
SRC1[1:0]_CFG1
SRC1[1:0]_CFG2
SRC1[1:0]_CFG3
SRC6[2:0]_CFG4
SRC6[2:0]_CFG5
SRC6[2:0]_CFG0
SRC6[2:0]_CFG1
SRC6[2:0]_CFG2
SRC6[2:0]_CFG3
X2_CFG4
X2_CFG5
X2_CFG0
X2_CFG1
X2_CFG2
X2_CFG3
TSSC[3:0]_CFG0
TSSC[3:0]_CFG1
TSSC[3:0]_CFG2
TSSC[3:0]_CFG3
TSSC[3:0]_CFG4
TSSC[3:0]_CFG5
6
SD1[3:0]_CFG0
SD1[3:0]_CFG1
SD1[3:0]_CFG2
SD1[3:0]_CFG3
SD1[3:0]_CFG4
SD1[3:0]_CFG5
SRC3[2:0]_CFG0
SRC3[2:0]_CFG1
SRC3[2:0]_CFG2
SRC3[2:0]_CFG3
SRC3[2:0]_CFG4
SRC3[2:0]_CFG5
SRC0[1:0]_CFG4
SRC0[1:0]_CFG5
SRC0[1:0]_CFG0
SRC0[1:0]_CFG1
SRC0[1:0]_CFG2
SRC0[1:0]_CFG3
5
4
Bit #
SRC5[2:0]_CFG4
SRC5[2:0]_CFG5
SRC5[2:0]_CFG0
SRC5[2:0]_CFG1
SRC5[2:0]_CFG2
SRC5[2:0]_CFG3
PDPL3_CFG4
PDPL3_CFG5
PDPL3_CFG0
PDPL3_CFG1
PDPL3_CFG2
PDPL3_CFG3
SSOFFSET[5:0]_CFG4
SSOFFSET[5:0]_CFG5
SSOFFSET[5:0]_CFG0
SSOFFSET[5:0]_CFG1
SSOFFSET[5:0]_CFG2
SSOFFSET[5:0]_CFG3
25
3
SRC2[2:0]_CFG0
SRC2[2:0]_CFG1
SRC2[2:0]_CFG2
SRC2[2:0]_CFG3
SRC2[2:0]_CFG4
SRC2[2:0]_CFG5
2
NSSC[3:0]_CFG0
NSSC[3:0]_CFG1
NSSC[3:0]_CFG2
NSSC[3:0]_CFG3
NSSC[3:0]_CFG4
NSSC[3:0]_CFG5
SM[1:0]_CFG4
SM[1:0]_CFG5
SM[1:0]_CFG0
SM[1:0]_CFG1
SM[1:0]_CFG2
SM[1:0]_CFG3
SD0[3:0]_CFG0
SD0[3:0]_CFG1
SD0[3:0]_CFG2
SD0[3:0]_CFG3
SD0[3:0]_CFG4
SD0[3:0]_CFG5
1
SRC4[2:1]_CFG4
SRC4[2:1]_CFG5
SRC4[2:1]_CFG0
SRC4[2:1]_CFG1
SRC4[2:1]_CFG2
SRC4[2:1]_CFG3
PRIMSRC_CFG4
PRIMSRC_CFG5
PRIMSRC_CFG0
PRIMSRC_CFG1
PRIMSRC_CFG2
PRIMSRC_CFG3
SRC1[2]_CFG0
SRC1[2]_CFG1
SRC1[2]_CFG2
SRC1[2]_CFG3
SRC1[2]_CFG4
SRC1[2]_CFG5
0
IDT5V49EE703
CLOCK SYNTHESIZER
PLL0 Spread Spectrum Control
Output Divide Source Selection
PRIMSRC - primary source -
crystal or ICLOCK
0 = crystal/REFIN
1 = CLKIN
SM = switch mode
0x = manual
10 = reserved
11 = auto-revertive
PDPL3 - PLL3 shutdown
0 = normal
1 = shut down
SRC = MUX control bit prior to
DIV#
SRC0[1:0]
00 - DIV1
01 - DIV3
10 - Reference input
SRC1/SRC2/SRC3..SRC5
000 - DIV1
001 - DIV3
010 - Reference input
011 - Reserved
100 - PLL0
101 - PLL1
110 - PLL2
111 - PLL3
SRC6
000 - Reserved
001 - Reserved
010 - Reference input
011 - Reserved
100 - Reserved
101 - PLL1
110 - Reserved
111 - Reserved
Quiet MUX
Description
REV F 022310