MK20DX128ZVLQ10 Freescale Semiconductor, MK20DX128ZVLQ10 Datasheet - Page 50
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MK20DX128ZVLQ10
Manufacturer Part Number
MK20DX128ZVLQ10
Description
KINETIS 128KFLEX USB
Manufacturer
Freescale Semiconductor
Specifications of MK20DX128ZVLQ10
Processor Series
K20
Core
ARM Cortex M4
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
128 KB
Interface Type
USB, CAN, SPI, I2C, UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
2
Number Of Timers
2
Operating Supply Voltage
1.71 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
LQFP-144
Operating Temperature Range
- 40 C to + 105 C
Processor To Be Evaluated
MK20DX128ZVLQ10
Supply Current (max)
185 mA
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MK20DX128ZVLQ10
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Peripheral operating requirements and behaviors
6.6.3.2 12-bit DAC operating behaviors
1. Settling within ±1 LSB
2. The INL is measured for 0+100mV to V
3. The DNL is measured for 0+100 mV to V
4. The DNL is measured for 0+100mV to V
5. Calculated by a best fit curve from V
50
I
I
t
DDA_DACL
V
Symbol
DDA_DAC
CCDACLP
V
V
t
t
PSRR
DACHP
OFFSET
DACLP
dacouth
DNL
DNL
dacoutl
T
Rop
T
BW
INL
SR
CT
E
HP
P
CO
GE
G
Supply current — low-power mode
Supply current — high-speed mode
Full-scale settling time (0x080 to 0xF7F) —
low-power mode
Full-scale settling time (0x080 to 0xF7F) —
high-power mode
Code-to-code settling time (0xBF8 to
0xC08) — low-power mode and high-speed
mode
DAC output voltage range low — high-
speed mode, no load, DAC set to 0x000
DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
Integral non-linearity error — high speed
mode
Differential non-linearity error — V
V
Differential non-linearity error — V
VREF_OUT
Offset error
Gain error
Power supply rejection ratio, V
Temperature coefficient offset voltage
Temperature coefficient gain error
Output resistance load = 3 kΩ
Slew rate -80h→ F7Fh→ 80h
Channel to channel cross talk
3dB bandwidth
Description
• High power (SP
• Low power (SP
• High power (SP
• Low power (SP
K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Table 33. 12-bit DAC operating behaviors
LP
LP
HP
HP
)
)
)
)
SS
+100 mV to V
DDA
DACR
DACR
DACR
DACR
DACR
> = 2.4 V
−100 mV
−100 mV with V
−100 mV
> 2
=
DACR
V
−100
−100 mV
0.05
Min.
550
DACR
1.2
60
40
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DDA
> 2.4V
0.000421
±0.4
±0.1
0.12
Typ.
100
0.7
3.7
1.7
15
—
—
—
—
—
—
—
—
—
—
—
V
Max.
±0.8
±0.6
150
700
200
100
250
DACR
-80
30
±8
±1
±1
90
—
—
—
—
—
—
1
Freescale Semiconductor, Inc.
%FSR/C
%FSR
%FSR
μV/C
V/μs
LSB
LSB
LSB
Unit
kHz
mV
mV
μA
μA
dB
dB
μs
μs
μs
Ω
Notes
1
1
1
2
3
4
5
5
6