MT41J128M16HA-15E IT:D Micron Technology Inc, MT41J128M16HA-15E IT:D Datasheet - Page 125

• Manufacturer Part Number: MT41J128M16HA-15E IT:D
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J128M16HA-15E IT:D

• Organization: 128Mx16
• Address Bus: 17b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: -40C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Pin Count: 96
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

Write Leveling
Figure 46: Write Leveling Concept
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
Destination
Source
Destination
Differential DQS
Differential DQS
Differential DQS
CK#
CK#
CK#
DQ
DQ
CK
CK
CK
Tn
Tn
T0
For better signal integrity, DDR3 SDRAM memory modules adopted fly-by topology for
the commands, addresses, control signals, and clocks. Write leveling is a scheme for the
memory controller to adjust or deskew the DQS strobe (DQS, DQS#) to CK relationship
at the DRAM with a simple feedback feature provided by the DRAM. Write leveling is
generally used as part of the initialization process, if required. For normal DRAM opera-
tion, this feature must be disabled. This is the only DRAM operation where the DQS
functions as an input (to capture the incoming clock) and the DQ function as outputs
(to report the state of the clock). Note that nonstandard ODT schemes are required.
The memory controller using the write leveling procedure must have adjustable delay
settings on its DQS strobe to align the rising edge of DQS to the clock at the DRAM pins.
This is accomplished when the DRAM asynchronously feeds back the CK status via the
DQ bus and samples with the rising edge of DQS. The controller repeatedly delays the
DQS strobe until a CK transition from 0 to 1 is detected. The DQS delay established
through this procedure helps ensure
that use fly-by topology by deskewing the trace length mismatch. A conceptual timing
of this procedure is shown.
Push DQS to capture
0–1 transition
T0
T0
T1
T1
T1
T2
0
125
T2
T2
1
T3
t
DQSS,
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T3
T3
T4
t
DSS, and
2Gb: x4, x8, x16 DDR3 SDRAM
0
T4
T4
1
t
T5
DSH specifications in systems
© 2006 Micron Technology, Inc. All rights reserved.
T5
T5
T6
Write Leveling
Don’t Care
T6
T6
T7