DS32508N+ Maxim Integrated Products, DS32508N+ Datasheet - Page 41

• Manufacturer Part Number: DS32508N+
• Description: IC LIU DS3/E3/STS-1 484-BGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS32508N+

• Protocol: IEEE 1149.1
• Voltage - Supply: 1.8V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 484-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -

Table 8-11. CLAD Clock Source Settings
Table 8-12. CLAD Clock Pin Output Settings
*
8.7.2 One-Second Reference Generator
The one-second reference signal can be used to update performance monitoring registers on a precise one-
second interval. The generated internal signal is a 50% duty cycle signal that is divided down from the indicated
reference signal. The low to high edge on this signal sets the GLOBAL.SRL:1SREFL latched one-second bit, which
can generate an interrupt if enabled. The low to high edge is used to initiate a performance monitor register update
when GLOBAL.CR1:GPM[1:0] = 1X. The internal one-second reference can be output on the GPIOB3 pin by
setting GLOBAL.CR1:G1SROE. The source for the one second reference is set by GLOBAL.CR1:G1SRS[3:0]. The
DS3, E3, and STS-1 reference clocks are sourced from the CLAD, if the CLAD is configured to generate them, or
from the CLKA, CLKB ,and CLKC pins, respectively.
Table 8-13. Global One-Second Reference Source
When CLAD[6:4] = 000, CLKA, CLKB, and CLKC are inputs and CLKD is held low.
CLAD[6:4]
CLAD[3:0]*
000
001
010
011
100
101
110
111
XXX0
XXX1
XX0X
XX1X
X0XX
X1XX
0XXX
1XXX
G1SRS[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
77.76MHz input
19.44MHz input
38.88MHz input
12.80MHz input
STS-1 input
Don't Care
DS3 input
REFCLK
E3 input
PLL-A output
Low output
CLKA PIN
—
—
—
—
—
—
DS3 output
DS3 output
DS3 output
DS3 output
DS3 output
DS3 output
DS3 output
DS3 input
STS-1 reference clock
DS3 reference clock
CLKA
E3 reference clock
Port 10 TCLK
Port 11 TCLK
Port 12 TCLK
Port 1 TCLK
Port 2 TCLK
Port 3 TCLK
Port 4 TCLK
Port 5 TCLK
Port 6 TCLK
Port 7 TCLK
Port 8 TCLK
Port 9 TCLK
SOURCE
Disabled
PLL-B output
Low output
CLKB PIN
—-
—
—
—
—
—
41 of 130
E3 output
E3 output
E3 output
E3 output
E3 output
E3 output
E3 output
E3 input
CLKB
STS-1 output
STS-1 output
STS-1 output
STS-1 output
STS-1 output
STS-1 output
STS-1 output
STS-1 input
PLL-C output
CLKC
Low output
CLKC PIN
—
—
—
—
—
—
77.76 or 19.44MHz output
77.76 or 19.44MHz output
77.76 or 19.44MHz output
77.76 or 19.44MHz output
77.76 or 19.44MHz output
77.76 or 19.44MHz output
77.76 or 19.44MHz output
DS32506/DS32508/DS32512
Low output
CLKD
PLL-D output
Low output
CLKD PIN
—
—
—
—
—
—