DS3154+ Maxim Integrated Products, DS3154+ Datasheet - Page 8

• Manufacturer Part Number: DS3154+
• Description: IC LIU DS3/E3/STS1 QUAD 144CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS3154+

• Number Of Drivers/receivers: 4/4
• Protocol: IEEE 1149.1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 144-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3. HARDWARE MODE AND CPU BUS MODE
The DS315x can operate in either hardware mode or CPU bus mode. In hardware mode, pulling configuration input
pins high or low does all configuration, and all status information is reported on status output pins. Internal registers
are not accessible in hardware mode. The device is configured for hardware mode when the HW pin is wired high
(HW = 1).
In CPU bus mode, most of the configuration and status pins used in hardware mode are reassigned to be address,
data, and control lines that provide a glueless interface to an 8-bit microprocessor bus. Through the CPU bus, an
external processor can access a set of internal registers. Setting configuration register bits high or low can do
configuration, and status information can be read from status register bits. Events indicated by status register bits
can also activate the interrupt output pin (INT), if configured to do so by a set of interrupt-enable bits. A few
configuration and status pins are active in hardware mode and CPU bus mode to support specialized applications,
such as protection switching. The device is configured for CPU bus mode when the HW pin is wired low (HW = 0).
With the exception of the HW pin, configuration and status pins available in hardware mode have corresponding
register bits in the CPU bus mode. The hardware mode pins and the CPU bus mode register bits have identical
names and functions, with the exception that all register bits are active high. For example, LOS is indicated by the
receiver on the RLOS pin (active low) in hardware mode and the RLOS register bit (active high) in CPU bus mode.
The few configuration input pins that are active in CPU bus mode also have corresponding register bits. In these
cases, the actual configuration is the logical OR of pin assertion and register bit assertion. For example, the
transmitter output driver is tri-stated if the TTS pin is asserted (i.e., low) or the TTS register bit is asserted (high).
Figure 3-1
lists the pins that are active in each mode.
Figure 3-1. Hardware Mode Block Diagram
RXPn
RXNn
TDMn
TXPn
TXNn
and
V
V
DD
SS
Figure 3-2
Supply
Power
Analog
Local
Loopback
RMONn
TTSn
Monitor
Driver
show block diagrams of the DS315x in hardware mode and in CPU bus mode.
T3MCLK E3MCLK STMCLK
Loopback Control
LLBn
Automatic
Equalizer
Adaptive
Control
Clock Mux
Gain
+
ALOS
RLBn
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
squelch
TLBOn
Recovery
Clock &
Data
RJAn
TJAn
8 of 61
Digital
Local
Loopback
TBIN
Remote
Loopback
Encoder
Digital LOS
B3ZS/HDB3
B3ZS/
HDB3
Detector
Decoder
RLOSn
RBIN
AIS, 100100…,
Configuration
PRBS Pattern
Generation
Global
TDSAn,
TDSBn
Detector
PRBS
Drivers,
Output
Clock
Invert
Clock
Invert
PRBSn
RTSn
RPOSn/RDATn
RNEGn/RLCVn
RCLKn
RCINV
HIZ
RST
HW
E3Mn
STSn
TPOSn/TDATn
TNEGn
TCLKn
TCINV
Semiconductor
DS315x
Dallas
Table 4-A