DS90CR562MTD National Semiconductor, DS90CR562MTD Datasheet - Page 10

IC RCVR LVDS FPD 18BIT 48-TSSOP

DS90CR562MTD

Manufacturer Part Number
DS90CR562MTD
Description
IC RCVR LVDS FPD 18BIT 48-TSSOP
Manufacturer
National Semiconductor
Type
Receiverr
Datasheet

Specifications of DS90CR562MTD

Number Of Drivers/receivers
0/3
Protocol
RS644
Voltage - Supply
4.5 V ~ 5.5 V
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
*DS90CR562MTD

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TxIN
TxOUT+
TxOUT−
FPSHIFT IN
TxCLK OUT+
TxCLK OUT−
PWR DOWN
DS90CR561 Pin Description—FPD Link Transmitter
AC Timing Diagrams
SW — Setup and Hold Time (Internal data sampling window)
TCCS — Transmitter Output Skew
RSKM
Cable Skew — Typically 10 ps–40 ps per foot
Pin Name
Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)
I/O
O
O
O
O
I
I
I
No.
21
FIGURE 17. Transmitter LVDS Output Pulse Position Measurement
3
3
1
1
1
1
TTL Level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines (FPLINE,
FPFRAME, DRDY). (Also referred to as HSYNC, VSYNC and DATA ENABLE.)
Positive LVDS differential data output
Negative LVDS differential data output
TTL level clock input. The rising edge acts as data strobe.
Positive LVDS differential clock output
Negative LVDS differential clock output
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power
down.
(Continued)
FIGURE 18. Receiver LVDS Input Skew Margin
10
Description
DS012470-26
DS012470-25

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