MC145574AAC Freescale Semiconductor, MC145574AAC Datasheet - Page 29

• Manufacturer Part Number: MC145574AAC
• Description: IC TRANSCEIVER ISDN 32-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Transceiverr

Specifications of MC145574AAC

• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Protocol: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
4.3.2
4.3.3
4.3.4
4.3.5
NT IDL2 Master
As mentioned previously, the normal configuration for the MC145574, when configured as an NT, is
as an IDL2 slave. However, in order to facilitate testing of the environment in which the MC145574
resides, the capability exists to configure the chip as an NT IDL2 master. In this mode of operation,
the chip outputs FSC and DCL. These signals are divided down from the 15.36 MHz crystal input
XTALIN and hence are synchronous with it. The NT IDL2 master mode also finds use in testing PC–
based local area networks or in passive bus configurations. In these environments, it may be required
to configure one of the TEs to act as an NT. The NT IDL2 master enables the user to do this. Writing
a 1 to BR7(3) or OR8(3), or pulling high the M/S pin, puts the NT into the IDL2 master mode. Note
that a software or a hardware reset reconfigures the NT as an IDL2 slave.
When the MC145574 is acting as an NT IDL2 master, the DCL can be programmed to output one
of four frequencies. The DCL rate is determined by BR7(2) and BR13(5). In the NT IDL2 master mode,
the DCL is obtained by dividing down from the 15.36 MHz crystal. Application of a software or a hard-
ware reset will reset BR7(2) and BR13(5) to 0. Note that these bits have no application when the
MC145574 is an NT IDL2 slave.
TE IDL2 Master
This is the normal mode of operation for the MC145574 when active as an NT. In this mode, the
MC145574 derives its timing from the inbound data from the NT. When the TE is receiving either INFO 2
or INFO 4 from the NT, it adaptively phase–locks onto it. The TE sets the FSYNC bit (NR1(0)) high
when this frame synchronization has been achieved. When this occurs, the TE outputs FSC, DCL,
and D out synchronous with the inbound INFO 2 or INFO 4. If the TE is receiving INFO 2, it outputs
“idle 1s” on D out in the B1, B2, and D channel timeslots. If the TE is receiving INFO 4, it outputs valid
data in these timeslots.
Note that when the TE has reached its fully active state, it internally sets the activate indication bit
(NR1(3)). (The active state for a TE is when it is receiving INFO 4 from the NT, has phase–locked
onto it, and is transmitting back INFO 3 to the NT.) In the TE IDL2 master mode, BR7(2) and BR7(3)
determine the output DCL rate. See description of BR7 bits 1 and 2 in Section 9.9.
TE IDL2 Master Free Run
The capability exists in the MC145574 to configure the chip as a TE operating in the IDL2 master
free run mode. This is done by setting BR7(3) to a 1. In this mode, the TE sends out a DCL and FSC
regardless of the state of the frame synchronization bit (NR1(0)). If NR1(0) is low, then FSC and DCL
are derived from the crystal in the same way as in the NT IDL2 master mode. Upon achieving frame
synchronization (i.e., the TE is receiving either INFO 2 or INFO 4 from the NT, has phase–locked
onto it, and has set NR1(0)), FSC and DCL will become synchronous to the inbound INFO 2 or
INFO 4 from the NT. The TE IDL2 master mode has the capability of providing four clock rates:
2.56 MHz, 2.048 MHz, 1.536 MHz, and 512 kHz.
TE IDL2 Slave
The TE slave–slave mode should be selected when the device is to be used on the T–interface of
an NT2. In this mode, the IDL2 is in the slave mode, and D channel data is continuously transmitted/re-
ceived to/from the T–interface. The D channel access algorithm is disabled in this mode.
In this mode, the frame sync and serial clock are inputs. The IDL2 circuitry incorporates buffering
to accommodate any phase relationship between the frame sync and the received S/T frame. The
buffering is able to absorb low–frequency wander between the IDL2 frame sync and the S/T frame.
The wander absorption capability exceeds the requirement of Q.502, which defines wander as 18 s
peak–to–peak at frequencies below 10 Hz over a 24–hour period.
Freescale Semiconductor, Inc.
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MC145574
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