AT90USB646-16MU Atmel, AT90USB646-16MU Datasheet - Page 15
![Microcontrollers (MCU) AVR USB 64K FLASH5V](/photos/39/69/396955/mlf_qfn-64_sml.jpg)
AT90USB646-16MU
Manufacturer Part Number
AT90USB646-16MU
Description
Microcontrollers (MCU) AVR USB 64K FLASH5V
Manufacturer
Atmel
Datasheet
1.AT90USB1287-16MU.pdf
(30 pages)
Specifications of AT90USB646-16MU
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
64 KB
Data Ram Size
4 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN-64
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / Rohs Status
Details
Other names
AT90USB646-MU
7593GS–AVR–03/08
Mnemonics
MOVW
SWAP
BRVC
BSET
BCLR
ELPM
ELPM
ELPM
BRIE
BRID
ROR
MOV
ROL
ASR
SEC
SEN
SEH
LPM
LPM
LPM
LSR
BST
BLD
CLC
CLN
SEZ
CLZ
SES
CLS
SEV
CLV
SET
CLT
CLH
LDD
LDD
LDS
STD
STD
STS
SBI
CBI
LSL
SEI
CLI
LDI
LD
LD
LD
LD
LD
LD
LD
LD
LD
ST
ST
ST
ST
ST
ST
ST
ST
ST
Operands
Rd, Z+q
Rd,Y+q
Rd, X+
Rd, - X
Rd, Y+
Rd, - Y
Y+q,Rr
Z+q,Rr
Rd, Rr
Rd, Rr
Rd, Z+
X+, Rr
- X, Rr
Y+, Rr
- Y, Rr
Rd, Z+
Rd, Z+
Rd, -Z
Z+, Rr
Rd, K
Rd, X
Rd, Y
Rd, Z
-Z, Rr
Rd, Z
Rd, Z
Rd, b
Rd, k
X, Rr
Y, Rr
Rr, b
Z, Rr
k, Rr
P,b
P,b
Rd
Rd
Rd
Rd
Rd
Rd
s
s
k
k
k
BIT AND BIT-TEST INSTRUCTIONS
DATA TRANSFER INSTRUCTIONS
Load Program Memory and Post-Inc
Branch if Overflow Flag is Cleared
Clear Twos Complement Overflow
Extended Load Program Memory
Extended Load Program Memory
Extended Load Program Memory
Set Twos Complement Overflow.
Store Indirect with Displacement
Store Indirect with Displacement
Load Indirect with Displacement
Load Indirect with Displacement
Clear Half Carry Flag in SREG
Set Half Carry Flag in SREG
Rotate Right Through Carry
Branch if Interrupt Disabled
Bit Store from Register to T
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Branch if Interrupt Enabled
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Rotate Left Through Carry
Bit load from T to Register
Move Between Registers
Clear Bit in I/O Register
Global Interrupt Disable
Load Direct from SRAM
Global Interrupt Enable
Clear Signed Test Flag
Load Program Memory
Load Program Memory
Set Bit in I/O Register
Store Direct to SRAM
Arithmetic Shift Right
Set Signed Test Flag
Copy Register Word
Clear Negative Flag
Logical Shift Right
Set Negative Flag
Logical Shift Left
Clear T in SREG
Load Immediate
Clear Zero Flag
Set T in SREG
Description
Swap Nibbles
Set Zero Flag
Store Indirect
Store Indirect
Store Indirect
Load Indirect
Load Indirect
Load Indirect
Clear Carry
Flag Clear
Set Carry
Flag Set
Rd ← (RAMPZ:Z), RAMPZ:Z ←RAMPZ:Z+1
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
if (V = 0) then PC ← PC + k + 1
if ( I = 1) then PC ← PC + k + 1
if ( I = 0) then PC ← PC + k + 1
Rd(n+1) ← Rd(n), Rd(0) ← 0
Rd(n) ← Rd(n+1), Rd(7) ← 0
Rd(n) ← Rd(n+1), n=0..6
Rd ← (X), X ← X + 1
Rd ← (Y), Y ← Y + 1
Rd+1:Rd ← Rr+1:Rr
X ← X - 1, Rd ← (X)
Y ← Y - 1, Rd ← (Y)
(X) ← Rr, X ← X + 1
(Y) ← Rr, Y ← Y + 1
(Z) ← Rr, Z ← Z + 1
Z ← Z - 1, Rd ← (Z)
X ← X - 1, (X) ← Rr
Y ← Y - 1, (Y) ← Rr
Rd ← (Z), Z ← Z+1
Z ← Z - 1, (Z) ← Rr
Rd ← (Z), Z ← Z+1
R0 ← (RAMPZ:Z)
SREG(s) ← 1
SREG(s) ← 0
Rd ← (Y + q)
Rd ← (Z + q)
I/O(P,b) ← 1
I/O(P,b) ← 0
(Y + q) ← Rr
(Z + q) ← Rr
Operation
Rd(b) ← T
T ← Rr(b)
Rd ← (X)
Rd ← (Y)
Rd ← (k)
Rd ← (Z)
R0 ← (Z)
Rd ← (Z)
Rd ← (Z)
Rd ← Rr
Rd ← K
(X) ← Rr
(Y) ← Rr
(Z) ← Rr
(k) ← Rr
C ← 1
C ← 0
N ← 1
N ← 0
S ← 1
S ← 0
V ← 1
V ← 0
H ← 1
H ← 0
Z ← 1
Z ← 0
T ← 1
T ← 0
I ← 1
I ← 0
AT90USB64/128
SREG(s)
SREG(s)
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Flags
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
C
C
N
N
S
S
V
V
H
H
T
Z
Z
T
T
I
I
#Clocks
1/2
1/2
1/2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
15