LH79525N0Q100A1 NXP Semiconductors, LH79525N0Q100A1 Datasheet - Page 20

• Manufacturer Part Number: LH79525N0Q100A1
• Description: Microcontrollers (MCU) LCD USB ETH'NET MMU
• Manufacturer: NXP Semiconductors

Specifications of LH79525N0Q100A1

• Data Bus Width: 32 bit
• Program Memory Type: ROMLess
• Data Ram Size: 16 KB
• Interface Type: I2C, I2S, IrDA, SSP, UART, USB
• Maximum Clock Frequency: 76.205 MHz
• Number Of Programmable I/os: 86
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Lead Free Status / Rohs Status: Details
• Other names: LH79525N0Q100A1;55

LH79524/LH79525
SYSTEM DESCRIPTIONS
ARM720T Processor
the ARM720T cached core with an Advanced High-Per-
formance Bus (AHB) interface. The ARM720T features:
• 32-bit ARM720T RISC Core
• 8 kB Cache
• MMU (Windows CE enabled)
ARM7T family of processors. For more information, see
the ARM document, ‘ARM720T (Rev 3) Technical
Reference Manual’, available on ARM’s website at
www.ARM.com.
20
PIN NO.
The LH79524/LH79525 microcontrollers feature
The core processor for both is a member of the
157
158
159
Table 9. LH79525 LCD Data Multiplexing
PIN NAME
LCDVD2
LCDVD1
LCDVD0
SWITCHER
WIRELESS
ROUTER/
SINGLE PANEL
MUSTN3
MUSTN2
Figure 4. LH79524/LH79525 Application Diagram Example
CODEC
STN MONO 4-BIT
SENSOR
ARRAY
UART
A/D
I
ETHERNET
2
S
DUAL PANEL
MAC
MUSTN3
MUSTN2
TRANSCEIVER
ETHERNET
NXP Semiconductors
Rev. 01 — 16 July 2007
UART
USB
LH79524/LH79525
LCD
MATRIX
STN/TFT,
AD-TFT
1
4
7
*
KEY
ical Memory (PA) addresses to virtual memory
addresses. This allows physical memory, which is
constrained by hardware to specific addresses, to be
reorganized at addresses identified by the user. These
user identified locations are called Virtual Addresses
(VA). When the MMU is enabled, Code and Data must
be built, loaded, and executed using Virtual Addresses
which the MMU translates to Physical Addresses. In
addition, the user may implement a memory protection
scheme by using the features of the MMU. Address
translation and memory protection services provided
by the MMU are controlled by the user. The MMU
is directly controlled through the System Control
Coprocessor, Coprocessor 15 (CP15). The MMU is
indirectly controlled by a Translation Table (TT) and
Page Tables (PT) prepared by the user and estab-
lished using a portion of physical memory dedicated by
the user to storing the TT and PT’s.
2
5
8
0
GPIO
The LH79524/LH79525 MMU allows mapping Phys-
3
6
9
#
TOUCH SCREEN
A/D
SSP
SERIAL
EEPROM
SRAM or
SDRAM
BOOT
ROM
Preliminary data sheet
FLASH
System-on-Chip
LH79525-19A