ST92T141K4M6 STMicroelectronics, ST92T141K4M6 Datasheet - Page 112

• Manufacturer Part Number: ST92T141K4M6
• Description: Microcontrollers (MCU) OTP EPROM 16K SPI
• Manufacturer: STMicroelectronics

Specifications of ST92T141K4M6

• Data Bus Width: 8 bit, 16 bit
• Program Memory Type: EPROM
• Program Memory Size: 16 KB
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 2
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-34
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / Rohs Status: No

ST92141 - EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)
R253 - Read/Write
Register Page: 28
Reset Value: 0000 0000 (00h)
Bit 7 = OC1E Output Compare 1 Enable.
0: Output Compare 1 function is enabled, but the
1: Output Compare 1 function is enabled, the
Bit 6 = OC2E Output Compare 2 Enable.
0: Output Compare 2 function is enabled, but the
1: Output Compare 2 function is enabled, the
Bit 5 = OPM One Pulse Mode.
0: One Pulse Mode is not active.
1: One Pulse Mode is active, the ICAP1 pin can be
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OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
OCMP1 pin is a general I/O.
OCMP1 pin is dedicated to the Output Compare
1 capability of the timer.
OCMP2 pin is a general I/O.
OCMP2 pin is dedicated to the Output Compare
2 capability of the timer.
used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
7
9
0
Bit 4 = PWM Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
Bit 3, 2 = CC[1:0] Clock Control.
The value of the timer clock depends on these bits:
Table 22. Clock Control Bits
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = EXEDG External Clock Edge.
This bit determines which type of level transition
on the external clock pin EXTCLK will trigger the
free running counter.
0: A falling edge triggers the free running counter.
1: A rising edge triggers the free running counter.
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.
CC1
0
0
1
1
CC0
0
1
0
1
External Clock (where
Timer Clock
INTCLK
INTCLK
INTCLK
available)
/ 4
/ 2
/ 8