LPC1833FET256,551 NXP Semiconductors, LPC1833FET256,551 Datasheet
LPC1833FET256,551
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LPC1833FET256,551 Summary of contents
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UM10430 LPC18xx ARM Cortex-M3 microcontroller Rev. 00.13 — 20 July 2011 Document information Info Content LPC18xx, LPC1850, LPC1830, LPC1820, LPC1810, LPC1857, LPC1853, Keywords LPC1837, LPC1833, LPC1827, LPC1825, LPC1823, LPC1822, LPC1817, LPC1815, LPC1813, LPC1812, LPC1810, ARM Cortex-M3, SPIFI, SCT, USB, Ethernet ...
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... NXP Semiconductors Revision history Rev Date Description 0.13 <tbd> Preliminary LPC18xx User manual. • Modifications: Location of C_CAN1 reset updated in the RGU (see • Pin P2_7 replaced by pin P2_9 as boot pin in • Pin P2_7 designated as ISP entry pin in • Boot ROM size increased to 64 kB. ...
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... NXP Semiconductors Revision history …continued Rev Date Description 0.08 <tbd> Preliminary LPC18xx User manual. Modifications: • Updated the reference clock for the frequency monitor register • Description of RTC calibration updated • USB0 clock source description added to • USB1 clock source description added to • ...
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UM10430 Chapter 1: Introductory information Rev. 00.13 — 20 July 2011 1.1 Introduction The LPC18xx are ARM Cortex-M3 based microcontrollers for embedded applications. The ARM Cortex- next generation core that offers system enhancements such as low power consumption, ...
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... NXP Semiconductors – Two 32 kB SRAM blocks with separate bus access. Both SRAM blocks can be powered down individually. – ROM containing boot code and on-chip software drivers. – 32-bit One-Time Programmable (OTP) memory for general-purpose customer use. On-chip memory (parts with on-chip flash) • ...
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... NXP Semiconductors – Two I Digital peripherals: • – External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash, and SDRAM devices. – LCD controller with DMA support and a programmable display resolution 1024H 768V. Supports monochrome and color STN panels and TFT color panels ...
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... NXP Semiconductors – Wake-up from Deep-sleep, Power-down, and Deep power-down modes via external interrupts and interrupts generated by battery powered blocks in the RTC power domain. – Brownout detect with four separate thresholds for interrupt and forced reset. – Power-On Reset (POR). • ...
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... NXP Semiconductors 1.4 Ordering information (parts with on-chip flash) Table 3. Ordering information (parts with on-chip flash) Type number Package Name Description plastic low profile ball grid array package; 256 balls; body 17 17 LPC1857FET256 LBGA256 LPC1857 LQFP208 <tbd> LPC1857 BGA180 <tbd> ...
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... NXP Semiconductors Table 4. Ordering options (parts with on-chip flash) Type SRAM Flash Flash total total bank A LPC1817 136 512 kB LPC1815 136 kB 768 kB 384 kB LPC1813 104 kB 512 kB 256 kB LPC1812 104 kB 512 kB 512 kB <Document ID> User manual Flash LCD Ethernet USB0 bank B (Host, ...
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... NXP Semiconductors 1.5 Block diagram (flashless parts LPC1850/30/20/10) SWD/TRACE PORT/JTAG TEST/DEBUG INTERFACE GPDMA ARM CORTEX-M3 AHB MULTILAYER MATRIX BRIDGE 0 BRIDGE 1 BRIDGE 2 MOTOR RI TIMER WWDT CONTROL (1) USART0 PWM USART2 UART1 USART3 SSP0 TIMER2 TIMER3 TIMER0 SSP1 C_CAN1 TIMER1 QEI SCU GIMA GPIO ...
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... NXP Semiconductors TEST/DEBUG INTERFACE ARM CORTEX-M3 GPDMA tem I-code D-code 0 1 bus bus bus Fig 2. LPC18xx AHB multilayer matrix connections (flashless parts) <Document ID> User manual (1) (1) (1) (1) ETHERNET USB0 USB1 LCD All information provided in this document is subject to legal disclaimers. Rev. 00.13 — 20 July 2011 ...
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... NXP Semiconductors 1.6 Block diagram (parts with on-chip flash) SWD/TRACE PORT/JTAG TEST/DEBUG INTERFACE GPDMA ARM CORTEX-M3 AHB MULTILAYER MATRIX BRIDGE 0 BRIDGE 1 BRIDGE 2 MOTOR RI TIMER WWDT CONTROL USART0 PWM USART2 UART1 USART3 TIMER2 SSP0 TIMER3 TIMER0 C_CAN1 SSP1 TIMER1 QEI SCU = connected to GPDMA ...
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... NXP Semiconductors TEST/DEBUG INTERFACE ARM CORTEX-M3 GPDMA System I-code D-code 0 bus bus bus AHB MULTILAYER MATRIX = master-slave connection (1) Not available on all parts (see Table Fig 4. AHB multilayer matrix master and slave connections <Document ID> User manual (1) (1) (1) ETHERNET USB0 USB1 1 4). ...
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UM10430 Chapter 2: LPC18xx Memory mapping Rev. 00.13 — 20 July 2011 2.1 How to read this chapter The available peripherals and their memories vary for different parts. Ethernet: available on LPC185x/3x. • USB0: available on LPC185x/3x/2x. • USB1: available ...
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... NXP Semiconductors Table 5. LPC185x/3x/2x/1x SRAM configuration Part Local SRAM Local SRAM Local LPC1850 LPC1830 LPC1820 LPC1810 LPC1857 <tbd> <tbd> LPC1853 <tbd> <tbd> LPC1837 <tbd> <tbd> LPC1833 <tbd> <tbd> LPC1827 <tbd> <tbd> LPC1825 <tbd> <tbd> LPC1823 <tbd> <tbd> LPC1822 <tbd> <tbd> LPC1817 < ...
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... NXP Semiconductors Table 6. LPC185x/3x/2x/1x Flash configuration Part Flash bank A Flash bank A 256 kB 128 kB 0x1A00 0000 0x1A04 000 LPC1815 yes yes LPC1813 yes no LPC1812 yes yes 2.3.3 Bit banding Remark: Bit banding can not be used with the MAC_RWAKE_FRFLT register (see Section 22.6.10). ...
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... NXP Semiconductors 2.5 Memory map (flashless parts LPC1850/30/20/10) 2000 0000 16 MB static external memory CS3 F00 0000 16 MB static external memory CS2 E00 0000 16 MB static external memory CS1 D00 0000 16 MB static external memory CS0 C00 0000 reserved 1800 0000 ...
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LPC1850/30/20/10 0x400F 0000 reserved 0x400E 5000 APB3 ADC1 0x400E 4000 peripherals ADC0 0x400E 3000 C_CAN0 0x400E 2000 DAC 0x400E 1000 I2C1 0x400E 0000 0x400C 8000 ...
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... NXP Semiconductors 2.6 Memory map (parts with on-chip flash) 0x2000 0000 16 MB static external memory CS3 0x1F00 0000 16 MB static external memory CS2 0x1E00 0000 16 MB static external memory CS1 0x1D00 0000 16 MB static external memory CS0 0x1C00 0000 reserved 0x1B08 0000 ...
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LPC185x/3x/2x/1x 0x400F 0000 reserved 0x400E 5000 ADC1 0x400E 4000 ADC0 0x400E 3000 APB3 C_CAN0 0x400E 2000 peripherals DAC 0x400E 1000 I2C1 0x400E 0000 0x400D 0000 ...
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... NXP Semiconductors <Document ID> User manual Chapter 2: LPC18xx Memory mapping All information provided in this document is subject to legal disclaimers. Rev. 00.13 — 20 July 2011 UM10430 © NXP B.V. 2011. All rights reserved 1164 ...
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UM10430 Chapter 3: LPC18xx Boot ROM Rev. 00.13 — 20 July 2011 3.1 How to read this chapter This chapter applies to flashless parts LPC1850/30/20/10 only. 3.2 Features The boot ROM memory includes the following features: ROM memory size is ...
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... NXP Semiconductors Table 7. Boot mode when OTP BOOT_SRC bits are programmed Boot mode BOOT_SRC BOOT_SRC bit 3 bit 2 Boot pins 0 0 UART 0 0 SPIFI 0 0 EMC 8-bit 0 0 EMC 16-bit 0 1 EMC 32-bit 0 1 USB0 0 1 USB1 0 1 SPI (SSP USART3 1 0 [1] The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI ...
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... NXP Semiconductors 3.3.1 AES capable devices AES capable products will normally always boot from a secure (encrypted) image and use CMAC authentication. However a special development mode allows booting from a plain text image. This development mode is active when the AES key has not been programmed ...
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... NXP Semiconductors CPU clock LPC 18 xx RESET = IRC 12 MHz = 1 check pins = > 9 BOOT _ SRC = 1 or pins = 0 BOOT _ SRC = 9 BOOT _ SRC = 6 or pins = 8 or pins = 5 UART 0 UART 3 USB 1 boot boot boot valid read Header Header ? AES capable and CMAC no active ? yes copy image to ...
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... NXP Semiconductors 3.3.3 Boot image format AES capable products with a programmed AES key will always boot from a secure image and use CMAC authentication. A secure image should always include a header. Non-AES capable products may boot from an image with header or execute directly from the boot source (when the boot source is memory mapped ...
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... NXP Semiconductors 3.3.4 Boot image creation 3.3.4.1 CMAC The CMAC algorithm is used to calculate a tag which is used for image authentication. The tag is stored in the header field HASH_VALUE. The authentication process is as follows: 1. Use the CMAC algorithm to generate the 128-bit tag. Truncate the tag to 64 MSB and insert this truncated tag in the header ...
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... NXP Semiconductors Fig 10. CMAC generation 3.3.4.2 UART boot mode Figure 11 details the boot-flow steps of the UART boot mode. The execution of this mode happens only if the boot mode is set accordingly (see boot modes As illustrated in • Baudrate = 115200 (UART divisor registers are programmed assuming a 12 MHz clock frequency) ...
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... NXP Semiconductors Fig 11. UART boot process 3.3.4.3 SPIFI boot mode Figure 12 details the boot-flow steps of the Quad SPI flash boot mode. The execution of this mode happens only if the boot mode is set accordingly (see boot modes Table 8). The SPIFI clock is 36 MHz. ...
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... NXP Semiconductors Setup clock SPIFI_SCK= 36MHz Fig 12. SPIFI boot process 3.3.4.4 EMC boot modes The EMC boot process follows the main flow shown in 72 MHz, and a non-AES capable LPC18xx will boot directly from EMC when the image does not contain a header. The EMC uses 8 wait states. ...
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... NXP Semiconductors 3.3.4.5 SPI boot mode The boot uses SSP0 in SPI mode. The SPI clock is 18 MHz. Figure 14 details the boot-flow steps of the SPI flash boot mode. The execution of this mode happens only if the boot mode is set accordingly (see boot modes Table 8) ...
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... NXP Semiconductors IRC12 RESET VDDREG GND supply ramp up processor status Fig 15. Boot process timing 3.3.6 ISP In-System programming (ISP) is programming or re-programming the on-chip SRAM memory, using the boot loader software and the USART0 serial port. This can be done when the part resides in the end-user board. ISP allows to load data into on-chip SRAM and execute code from on-chip SRAM. For details, see < ...
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UM10430 Chapter 4: LPC18xx Security features Rev. 00.13 — 20 July 2011 4.1 How to read this chapter All LPC18xx parts support AES decoding. 4.2 Features Decoding of external image data. • Secure storage of decoding keys. • Support for ...
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... NXP Semiconductors Vpp 3V3 Vdd 1V2 Fig 16. AES engine 4.4 AES API calls 4.4.1 Security API The security API controls the AES block. Table 11. Security API calls Function AES_API_Set_Mode AES_API_Load_Key_1 AES_API_Load_Key_2 AES_API_Load_Key_RNG <Document ID> User manual OTP0 RNG AES_key JTAG OTP controller ...
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... NXP Semiconductors Table 11. Security API calls Function AES_API_Load_Key_SW AES_API_Load_IV_SW AES_API_Load_IV_IC AES_API_Operate AES_API_Program_Key_1 AES_API_Program_Key_2 4.4.2 OTP memory The virgin OTP state is all zeros. This implies that a zero value can be overwritten by a one value, but a one value cannot be changed. Programming the OTP requires a higher voltage than reading. The read voltage is generated internally ...
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UM10430 Chapter 5: LPC18xx NVIC Rev. 00.13 — 20 July 2011 5.1 How to read this chapter Remark: This chapter describes the NVIC connections of parts LPC1850/30/20/10 Rev ‘A’. The available NVIC interrupt sources vary for different parts. • Ethernet ...
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... NXP Semiconductors 5.6 Interrupt sources Table 13 lists the interrupt sources for each peripheral function. Each peripheral device may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may represent more than one interrupt source, as noted. Exception numbers relate to where entries are stored in the exception vector table. ...
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... NXP Semiconductors Table 13. Connection of interrupt sources to the NVIC Interrupt Exception ID Number 5.7 Register description The following table summarizes the registers in the NVIC as implemented in the LPC18xx. The Cortex-M3 User Guide provides a functional description of the NVIC. Table 14. Register overview: NVIC (base address 0xE000 E000) ...
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... NXP Semiconductors Table 14. Register overview: NVIC (base address 0xE000 E000) Name Access Address Description offset ICER1 RW 0x184 Interrupt Clear-Enable Register 1. This register allows disabling interrupts and reading back the interrupt enables for specific peripheral functions. ISPR0 RW 0x200 Interrupt Set-Pending Register 0. This register allows changing the interrupt state to pending and reading back the interrupt pending state for specific peripheral functions ...
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UM10430 Chapter 6: LPC18xx Event router Rev. 00.13 — 20 July 2011 6.1 How to read this chapter Remark: This chapter applies to parts LPC1850/30/30/10 Rev ‘A’ only. Remark: The event router controls the wake-up process and various event inputs ...
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... NXP Semiconductors 6.4 Event router inputs Table 16. Event router inputs Event # Source 0 WAKEUP0 1 WAKEUP1 2 WAKEUP2 3 WAKEUP3 4 Alarm timer 5 RTC 6 BOD trip level 1 7 WWDT 8 Ethernet 9 USB0 10 USB1 11 SD/MMC 12 C_CAN0/1 13 GIMA output 25 14 GIMA output 26 15 QEI 16 GIMA output Reset 20 BOD trip level 2 ...
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... NXP Semiconductors 6.6 Register description Table 18. Register overview: Event router (base address 0x4004 4000) Name HILO EDGE - CLR_EN SET_EN STATUS ENABLE CLR_STAT SET_STAT 6.6.1 Level configuration register This register works in combination with the edge configuration register EDGE (see Table 21) to configure the level and edge detection for each input to the event router. ...
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... NXP Semiconductors Table 19. Level configuration register (HILO - address 0x4004 4000) bit description Bit Symbol 4 ATIMER_L 5 RTC_L 6 BOD_L 7 WWDT_L 8 ETH_L 9 USB0_L 10 USB1_L CAN_L <Document ID> User manual Value Description Level detect mode for alarm timer event. 0 Detect LOW level if bit 4 in the EDGE register is 0. Detect falling edge if bit 4 in the EDGE register is 1 ...
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... NXP Semiconductors Table 19. Level configuration register (HILO - address 0x4004 4000) bit description Bit Symbol 13 TIM2_L 14 TIM6_L 15 QEI_L 16 TIM14_L 18: RESET_L 31:20 - 6.6.2 Edge configuration register This register works in combination with the level configuration register HILO (see Table 19) to configure the level or edge detection for each input to the event router. ...
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... NXP Semiconductors When a HIGH level detect is active, the event router status bits cannot be cleared until the signal is LOW. When a rising edge detect is active, the event router status bit can be cleared right after the event has occurred. Table 21. Edge configuration register (EDGE - address 0x4004 4004) bit description ...
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... NXP Semiconductors Table 21. Edge configuration register (EDGE - address 0x4004 4004) bit description Bit Symbol 7 WWDT_E 8 ETH_E 9 USB0_E 10 USB1_E CAN_E 13 TIM2_E 14 TIM6_E <Document ID> User manual Value Description Edge/level detect mode for WWDTD event. The corresponding bit in the EDGE register must be 0. ...
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... NXP Semiconductors Table 21. Edge configuration register (EDGE - address 0x4004 4004) bit description Bit Symbol 15 QEI_E 16 TIM14_E 18: RESET_E 31:20 - 6.6.3 Interrupt clear enable register Table 22. Interrupt clear enable register (CLR_EN - address 0x4004 4FD8) bit description Bit Symbol 0 WAKEUP0_CLREN Writing this bit clears the event enable bit 0 in the ...
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... NXP Semiconductors Table 22. Interrupt clear enable register (CLR_EN - address 0x4004 4FD8) bit description Bit Symbol 10 USB1_CLREN CAN_CLREN 13 TIM2_CLREN 14 TIM6_CLREN 15 QEI_CLREN 16 TIM14_CLREN 18: RESET_CLREN 31:20 - 6.6.4 Event set enable register Table 23. Event set enable register (SET_EN - address 0x4004 4FDC) bit description Bit Symbol ...
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... NXP Semiconductors Table 23. Event set enable register (SET_EN - address 0x4004 4FDC) bit description Bit Symbol 12 CAN_SETEN 13 TIM2_SETEN 14 TIM6_SETEN 15 QEI_SETEN 16 TIM14_SETEN 18: RESET_SETEN 31:20 - 6.6.5 Event status register Table 24. Interrupt status register (STATUS - address 0x4004 4FE0) bit description Bit Symbol 0 WAKEUP0_ST this bit shows that the WAKEUP0 event has been raised WAKEUP1_ST this bit shows that the WAKEUP1 event has been raised ...
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... NXP Semiconductors 6.6.6 Event enable register Table 25. Event enable register (ENABLE - address 0x4004 4FE4) bit description Bit Symbol 0 WAKEUP0_EN this bit shows that the WAKEUP0 event has been 1 WAKEUP1_EN this bit shows that the WAKEUP1 event has been 2 WAKEUP2_EN this bit shows that the WAKEUP2 event has been ...
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... NXP Semiconductors Table 25. Event enable register (ENABLE - address 0x4004 4FE4) bit description Bit Symbol 16 TIM14_EN 18: RESET_EN 31:20 - 6.6.7 Clear status register Table 26. Interrupt clear status register (CLR_STAT - address 0x4004 4FE8) bit description Bit Symbol 0 WAKEUP0_CLRST 1 WAKEUP1_CLRST 2 WAKEUP2_CLRST 3 WAKEUP3_CLRST 4 ATIMER_CLRST 5 RTC_CLRST 6 BOD_CLRST ...
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... NXP Semiconductors Table 26. Interrupt clear status register (CLR_STAT - address 0x4004 4FE8) bit description Bit Symbol 16 TIM14_CLRST 18: RESET_CLRST 31:20 - 6.6.8 Set status register Table 27. Interrupt set status register (SET_STAT - address 0x4004 4FEC) bit description Bit Symbol 0 WAKEUP0_SETST 1 WAKEUP1_SETST 2 WAKEUP2_SETST 3 WAKEUP3_SETST 4 ATIMER_SETST 5 RTC_SETST ...
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... NXP Semiconductors Table 27. Interrupt set status register (SET_STAT - address 0x4004 4FEC) bit description Bit Symbol 18: RESET_SETST 31:20 - <Document ID> User manual Description Reserved. Writing this bit sets the STATUS event bit 19 in the STATUS register. Reserved. All information provided in this document is subject to legal disclaimers. ...
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UM10430 Chapter 7: LPC18xx Configuration Registers (CREG) Rev. 00.13 — 20 July 2011 7.1 How to read this chapter Remark: This chapter applies to LPC1850/30/20/10 Rev ‘A’ only. The available peripherals vary for different parts. Ethernet: available on LPC1850/30. • ...
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... NXP Semiconductors 7.4 Register description Table 29. Register overview: Configuration registers (base address 0x4004 3000) Name Access Address offset IRCTRM RO 0x000 CREG0 R/W 0x004 PMUCON 0x008 - - 0x008 - 0x0FC M3MEMMAP R/W 0x100 - - 0x104 CREG1 RO 0x108 CREG2 RO 0x10C CREG3 RO 0x110 CREG4 RO 0x114 CREG5 R/W ...
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... NXP Semiconductors 7.4.2 CREG0 control register Table 31. CREG0 register (CREG0, address 0x4004 3004) bit description Bit Symbol 0 EN1KHZ 1 EN32KHZ 2 RESET32KHZ 3 32KHZPD USB0PHY 7:6 ALARMCTRL 9:8 BODLVL1 11:10 BODLVL2 31:12 - 7.4.3 Power mode control register For details on power mode selection, see <Document ID> ...
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... NXP Semiconductors Table 32. Power mode control register (PMUCON, address 0x4004 3008) bit description Bit Symbol 1:0 PMUCON 31:2 - 7.4.4 ARM Cortex-M3 memory mapping register Table 33. Memory mapping register (M3MEMMAP, address 0x4004 3100) bit description Bit Symbol 11:0 31:12 M3MAP 7.4.5 CREG5 control register Table 34 ...
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... NXP Semiconductors Table 35. DMA muxing register (DMAMUX, address 0x4004 311C) bit description Bit Symbol 3:2 DMAMUXCH1 5:4 DMAMUXCH2 7:6 DMAMUXCH3 9:8 DMAMUXCH4 11:10 DMAMUXCH5 13:12 DMAMUXCH6 15:14 DMAMUXCH7 <Document ID> User manual Chapter 7: LPC18xx Configuration Registers (CREG) Value Description Select DMA to peripheral connection for ...
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... NXP Semiconductors Table 35. DMA muxing register (DMAMUX, address 0x4004 311C) bit description Bit Symbol 17:16 DMAMUXCH8 19:18 DMAMUXCH9 21:20 DMAMUXCH10 23:22 DMAMUXCH11 25:24 DMAMUXCH12 27:26 DMAMUXCH13 29:28 DMAMUXCH14 <Document ID> User manual Chapter 7: LPC18xx Configuration Registers (CREG) Value Description Select DMA to peripheral connection for DMA peripheral 8 ...
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... NXP Semiconductors Table 35. DMA muxing register (DMAMUX, address 0x4004 311C) bit description Bit Symbol 31:30 DMAMUXCH15 7.4.7 ETB SRAM configuration register This register selects the interface that is used to the 16 kB block of RAM located at address 0x2000 C000. This RAM memory block can be accessed either by the ETB or be used as normal SRAM on the AHB bus ...
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... NXP Semiconductors Table 37. CREG6 control register (CREG6, address 0x4004 312C) bit description Bit Symbol 11 I2S0_TX_SCK_IN_ SEL 13 I2S0_RX_SCK_IN_ SEL 14 I2S1_TX_SCK_IN_ SEL 15 I2S1_RX_SCK_IN_ SEL 16 EMC_CLK_SEL 31 7.4.9 Part ID register Table 38. Part ID register (CHIPID, address 0x4004 3200) bit description Bit Symbol 31:0 ID <Document ID> User manual ...
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UM10430 Chapter 8: LPC18xx Power Management Controller (PMC) Rev. 00.13 — 20 July 2011 8.1 How to read this chapter The power management controller is identical on all LPC18xx parts. 8.2 General description The PMC implements the control sequences to ...
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... NXP Semiconductors As in active mode, low-power and normal modes can be selected. 8.2.3 Deep-sleep mode In Deep-sleep mode the CPU clock and peripheral clocks are shut down to save power; logic states and SRAM memory are maintained. All analog blocks and the BOD control circuit are powered down ...
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... NXP Semiconductors 8.3 Register description Table 39. Register overview: Power Mode Controller (PMC) (base address 0x4004 2000) Name PD0_SLEEP0_HW_ENA - PD0_SLEEP0_MODE 8.3.1 Hardware sleep event enable register PD0_SLEEP0_HW_ENA Table 40. Hardware sleep event enable register (PD0_SLEEP0_HW_ENA - address 0x4004 2000) bit description Bit Symbol 0 ENA_EVENT0 ...
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... NXP Semiconductors 8.4 Functional description 8.4.1 Run-time programming The PD0_SLEEP0_MODE register can be programmed at run-time to change the default power state of the LPC18xx after the next transition to a reduced-power state. The default state is Deep power-down corresponding to a reset value of the PD0_SLEEP0_MODE register of 0x003F FF7F. ...
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UM10430 Chapter 9: LPC18xx Clock Generation Unit (CGU) Rev. 00.13 — 20 July 2011 9.1 How to read this chapter Remark: This chapter describes the clock generation of parts LPC1850/30/20/10 Rev ‘A’ and parts LPC18xx (with on-chip flash). Note that ...
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... NXP Semiconductors CGU 12 MHz IRC RTCX1 32 kHz OSC RTCX2 XTAL1 CRYSTAL OSC XTAL2 ENET_RX_CLK ENET_TX_CLK GP_CLK Fig 17. CGU and CCU0/1 block diagram The CGU selects the inputs to the clock generators from multiple clock sources, controls the clock generation, and routes the outputs of the clock generators through the clock source bus to the output stages ...
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... NXP Semiconductors – Integer divider A: maximum division factor = 4 (see – Integer dividers maximum division factor = 16 (see – Integer divider E: maximum division factor = 256 (see The output stages select a clock source from the clock source bus for each base clock (see Table 46) ...
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... NXP Semiconductors Table 45. Available clock sources for clock generators with selectable inputs Clock sources 32 kHz oscillator IRC 12 MHz ENET_RX_CLK ENET_TX_CLK GP_CLKIN Crystal oscillator PLL0 (USB) PLL0 (audio) PLL1 IDIVA IDIVB IDIVC IDIVD IDIVE Table 46. Clock sources for output stages Output stages (d = default clock source yes (clock source available (clock ...
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... NXP Semiconductors Table 46. Clock sources for output stages Output stages (d = default clock source yes (clock source available (clock source not available)) Clock sources PLL1 IDIVA IDIVB IDIVC IDIVD IDIVE Oscillators, clock inputs 12 MHz IRC RTCX1 32 kHz OSC RTCX2 XTAL1 CRYSTAL OSC ...
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... NXP Semiconductors 9.5 Pin description Table 47. CGU pin description Pin name/ function name XTAL1 XTAL2 RTCX1 RTCX2 GP_CLKIN ENET_TX_CLK ENET_RX_CLK CLKOUT CGU_OUT0 CGU_OUT1 9.6 Register description The register addresses of the CGU are shown in Remark: The CGU is configured by the boot loader at reset and when waking up from Deep power-down to produce a 72 MHz clock using PLL1 ...
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... NXP Semiconductors Table 48. Register overview: CGU (base address 0x4005 0000) Name IDIVA_CTRL IDIVB_CTRL IDIVC_CTRL IDIVD_CTRL IDIVE_CTRL OUTCLK_0_CTRL OUTCLK_1_CTRL - OUTCLK_3_CTRL OUTCLK_4_CTRL OUTCLK_5_CTRL - OUTCLK_7_CTRL OUTCLK_8_CTRL OUTCLK_9_CTRL OUTCLK_10_CTRL OUTCLK_11_CTRL OUTCLK_12_CTRL OUTCLK_13_CTRL OUTCLK_14_CTRL OUTCLK_15_CTRL OUTCLK_16_CTRL OUTCLK_17_CTRL OUTCLK_18_CTRL OUTCLK_19_CTRL <Document ID> User manual Chapter 9: LPC18xx Clock Generation Unit (CGU) ...
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... NXP Semiconductors Table 48. Register overview: CGU (base address 0x4005 0000) Name OUTCLK_20_CTRL OUTCLK_21_CTRL to OUTCLK_24_CTRL OUTCLK_25_CTRL OUTCLK_26_CTRL OUTCLK_27_CTRL 9.6.1 Frequency monitor register The CGU can report the relative frequency of any operating clock. The clock to be measured must be selected by software, while the fixed-frequency IRC clock fref is used as the reference frequency ...
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... NXP Semiconductors Table 49. FREQ_MON register (FREQ_MON, address 0x4005 0014) bit description Bit Symbol 8:0 RCNT 22:9 FCNT 23 MEAS 28:24 CLK_SEL 31:29 - 9.6.2 Crystal oscillator control register The register XTAL_OSC_CONTROL contains the control bits for the crystal oscillator. Table 50. XTAL_OSC_CTRL register (XTAL_OSC_CTRL, address 0x4005 0018) bit ...
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... NXP Semiconductors Table 50. XTAL_OSC_CTRL register (XTAL_OSC_CTRL, address 0x4005 0018) bit description Bit Symbol 1 BYPASS 2 HF 31:3 - 9.6.3 PLL0 (for USB) registers The PLL0 provides a dedicated clock to the High-speed USB0 interface and to USB1. See Section 9.7.4.5 9.6.3.1 PLL0 (for USB) status register Table 51 ...
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... NXP Semiconductors Table 52. PLL0USB control register (PLL0USB_CTRL, address 0x4005 0020) bit description …continued Bit Symbol 3 DIRECTO 4 CLKEN FRM AUTOBLOCK 23:12 - 28:24 CLK_SEL 31:29 - 9.6.3.3 PLL0 (for USB) M-divider register Table 53. PLL0USB M-divider register (PLL0USB_MDIV, address 0x4005 0024) bit description Bit Symbol ...
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... NXP Semiconductors Table 53. PLL0USB M-divider register (PLL0USB_MDIV, address 0x4005 0024) bit description …continued Bit Symbol 21:17 SELP 27:22 SELI 31:28 SELR 9.6.3.4 PLL0 (for USB) NP-divider register Table 54. PLL0USB NP-divider register (PLL0USB_NP_DIV, address 0x4005 0028) bit description Bit Symbol 6:0 PDEC ...
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... NXP Semiconductors Table 56. PLL0AUDIO control register (PLL0AUDIO_CTRL, address 0x4005 0030) bit description …continued Bit Symbol 2 DIRECTI 3 DIRECTO 4 CLKEN FRM AUTOBLOCK 12 PLLFRAQ_ REQ 13 SEL_EXT 14 MOD_PD 23:15 - 28:24 CLK_SEL 31:29 - <Document ID> User manual Chapter 9: LPC18xx Clock Generation Unit (CGU) Value Description PLL0 direct input ...
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... NXP Semiconductors 9.6.4.3 PLL0 (for audio) M-divider register Table 57. PLL0AUDIO M-divider register (PLL0AUDIO_MDIV, address 0x4005 0034) bit description Bit Symbol 16:0 MDEC 21:17 SELP 27:22 SELI 31:28 SELR 9.6.4.4 PLL0 (for audio) NP-divider register Table 58. PLL0 AUDIO NP-divider register (PLL0AUDIO_NP_DIV, address 0x4005 0038) bit ...
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... NXP Semiconductors 9.6.5.2 PLL1 control register Table 61. PLL1_CTRL register (PLL1_CTRL, address 0x4005 0044) bit description Bit Symbol BYPASS FBSEL 7 DIRECT 9:8 PSEL AUTOBLOCK 13:12 NSEL 15:14 - <Document ID> User manual Chapter 9: LPC18xx Clock Generation Unit (CGU) Value Description PLL1 power down ...
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... NXP Semiconductors Table 61. PLL1_CTRL register (PLL1_CTRL, address 0x4005 0044) bit description …continued Bit Symbol 23:16 MSEL 27:24 CLK_SEL 31:28 - 9.6.6 Integer divider register A Table 62. IDIVA control register (IDIVA_CTRL, address 0x4005 0048) bit description Bit Symbol 3:2 IDIV 10:4 - <Document ID> User manual ...
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... NXP Semiconductors Table 62. IDIVA control register (IDIVA_CTRL, address 0x4005 0048) bit description …continued Bit Symbol 11 AUTOBLOCK 23:12 - 28:24 CLK_SEL 31:29 - 9.6.7 Integer divider register Table 63. IDIVB/C/D control registers (IDIVB_CTRL, address 0x4005 004C; IDIVC_CTRL, address 0x4005 0050; IDIVC_CTRL, address 0x4005 0054) bit description ...
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... NXP Semiconductors Table 63. IDIVB/C/D control registers (IDIVB_CTRL, address 0x4005 004C; IDIVC_CTRL, address 0x4005 0050; IDIVC_CTRL, address 0x4005 0054) bit description Bit Symbol 28:24 CLK_SEL 31:29 - 9.6.8 Integer divider register E Table 64. IDIVE control register (IDIVE_CTRL, address 0x4005 0058) bit description Bit Symbol ...
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... NXP Semiconductors Table 64. IDIVE control register (IDIVE_CTRL, address 0x4005 0058) bit description Bit Symbol 27:24 CLK_SEL 31:28 - 9.6.9 Output stage 0 control register This register controls the BASE_SAFE_CLK to the watchdog oscillator. The only possible clock source for this base clock is the IRC. ...
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... NXP Semiconductors Table 66. Output stage 1 control register (OUTCLK_1_CTRL, address 0x4005 0060) bit description Bit Symbol AUTOBLOCK 23:12 - 28:24 CLK_SEL 31:29 - 9.6.11 Output stage 3 control register These registers control base clocks 3 (USB1). Table 67. Output stage 3 control register (OUTCLK_3_CTRL, address 0x4005 0068) bit ...
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... NXP Semiconductors Table 67. Output stage 3 control register (OUTCLK_3_CTRL, address 0x4005 0068) bit description Bit Symbol 28:24 CLK_SEL 31:29 - 9.6.12 Output stage control registers These registers control base clocks 4 to 19. Table 68. Output stage control registers (OUTCLK_4_CTRL to OUTCLK_19_CTRL, address 0x4005 006C to 0x4005 00A8) bit description ...
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... NXP Semiconductors Table 68. Output stage control registers (OUTCLK_4_CTRL to OUTCLK_19_CTRL, address 0x4005 006C to 0x4005 00A8) bit description Bit Symbol 28:24 CLK_SEL 31:29 - 9.6.13 Output stage 20 register This register controls the clock output to the CLKOUT pin. All clock generator outputs can be monitored through this pin. ...
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... NXP Semiconductors Table 69. Output stage 20 control register (OUTCLK_20_CTRL, addresses 0x4005 00AC) bit description Bit Symbol 27:24 CLK_SEL 31:28 - 9.6.14 Output stage 25 register This register controls the clock output to the <tbd>. Table 70. Output stage 25 control register (OUTCLK_25_CTRL, addresses 0x4005 00C0) bit description ...
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... NXP Semiconductors Table 70. Output stage 25 control register (OUTCLK_25_CTRL, addresses 0x4005 00C0) bit description Bit Symbol 27:24 CLK_SEL 31:28 - 9.6.15 Output stage register This register controls the clock output to the spare CGU outputs pins CGU_OUT0 and CGU_OUT1. All clock generator outputs can be monitored through this pin. ...
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... NXP Semiconductors Table 71. Output stage control register (OUTCLK_26_CTRL to OUTCLK_27_CTRL, addresses 0x4005 00C4 to 0x4005 00C8) bit description Bit Symbol 27:24 CLK_SEL 31:28 - 9.7 Functional description 9.7.1 32 kHz oscillator The 32 kHz oscillator output is controlled by the CREG block (see and the Alarm timer are connected directly to the 32 kHz oscillator. ...
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... NXP Semiconductors Output clock range: 4.3 MHz to 550 MHz. • Programmable dividers: • – Pre-divider N ( – Feedback-divider ( – Post-divider ( • Programmable bandwidth (integrating action, proportional action, high frequency pole). • On-the-fly adjustment of the clock possible (dividers with handshake control). • Positive edge clocking. ...
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... NXP Semiconductors smaller than the so called “lock criterion” for more than seven consecutive input clock periods, the lock output switches from low to high. A single too large phase difference immediately resets the counter and causes the lock signal to drop (if it was high). ...
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... NXP Semiconductors Fout = Fcco = Fin (275 MHz Fcco 550 MHz, 4 kHz Fin 150 MHz) The feedback divider ratio is programmable: Feedback-divider M ( • 9.7.4.3.3 Mode 1b: Normal operating mode with post-divider and without pre-divider In normal operating mode 1b the pre-divider is bypassed. The operating frequencies are: Fout = Fcco /( Fin ...
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... NXP Semiconductors Table 74. System PLL divider ratio settings for 12 MHz Fout (MHz) <tbd> 9.7.4.5 Usage notes In order to set up the PLL0, follow these steps: 1. Power down the PLL0 by setting bit 1 in the PLL0_CTRL register to 1. This step is only needed if the PLL0 is currently enabled. ...
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... NXP Semiconductors 9.7.6.2 PLL1 description /N PFD 2 NSEL<1:0> DETECT analog section Fig 20. PLL1 block diagram The block diagram of this PLL is shown MHz. The input clock is fed directly to the Phase-Frequency Detector (PFD). This block compares the phase and frequency of its inputs, and generates a control signal when phase and/ or frequency do not match ...
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... NXP Semiconductors the PLL is not in lock. When the Power-down mode is terminated, the PLL will resume its normal operation and will make the lock signal high once it has regained lock on the input clock. 9.7.6.5 Selectable feedback divider clock To allow a trade-off to be made between functionality and power consumption, the feedback divider can be connected to either the CCO clock by setting FBSEL the output clock by setting FBSEL to 1 ...
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... NXP Semiconductors Non-integer mode In this mode the post-divider is enabled and the feedback divider is set to run directly on the CCO clock, which gives the following frequency dividers: Direct mode In this mode, the post-divider is disabled and the CCO clock is sent directly to the output, leading to the following frequency equation: ...
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... NXP Semiconductors 9.8 Example CGU configurations 9.8.1 Programming the CGU for Deep-sleep and Power-down modes Before the LPC18xx enters Deep-sleep or Power-down mode, the IRC must be programmed as the clock source in the control registers for all output stages (OUTCLK_0 to OUTCLK_27). In addition, the PLLs must be in Power-down mode. ...
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UM10430 Chapter 10: LPC18xx Clock Control Unit (CCU) Rev. 00.13 — 20 July 2011 10.1 How to read this chapter Remark: This chapter applies to parts LPC1850_30_20_10 rev “A”. Remark: The VADC is not available on parts LPC1850_30_10_10 rev “A”. ...
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... NXP Semiconductors Table 76. CCU1 branch clocks Base clock BASE_APB1_CLK CLK_APB1_BUS BASE_SPIFI_CLK CLK_SPIFI BASE_M3_CLK <Document ID> User manual Chapter 10: LPC18xx Clock Control Unit (CCU) Branch clock Description CLK_APB3_ADC0 Clock to the ADC0 register interface and ADC0 peripheral clock. CLK_APB3_ADC1 Clock to the ADC1 register interface and ADC1 peripheral clock ...
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... NXP Semiconductors Table 76. CCU1 branch clocks Base clock BASE_M3_CLK BASE_USB0_CLK CLK_USB0 BASE_USB1_CLK CLK_USB1 - BASE_ENET_CSR _CLK Table 77. CCU2 branch clocks Base clock BASE_APLL_CLK BASE_UART3_CLK BASE_UART2_CLK BASE_UART1_CLK BASE_UART0_CLK BASE_SSP1_CLK BASE_SSP0_CLK BASE_SDIO_CLK <Document ID> User manual Chapter 10: LPC18xx Clock Control Unit (CCU) Branch clock ...
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... NXP Semiconductors 10.5 Register description Table 78. Register overview: CCU1 (base address 0x4005 1000) Name PM BASE_STAT - CLK_APB3_BUS_CFG CLK_APB3_BUS_STAT CLK_APB3_I2C1_CFG CLK_APB3_I2C1_STAT CLK_APB3_DAC_CFG CLK_APB3_DAC_STAT CLK_APB3_ADC0_CFG CLK_APB3_ADC0_STAT CLK_APB3_ADC1_CFG CLK_APB3_ADC1_STAT CLK_APB3_CAN0_CFG CLK_APB3_CAN0_STAT - CLK_APB1_BUS_CFG CLK_APB1_BUS_STAT CLK_APB1_MOTOCONPWM_CFG CLK_APB1_MOTOCONPWM_STAT CLK_APB1_I2C0_CFG CLK_APB1_I2C0_STAT CLK_APB1_I2S_CFG CLK_APB1_I2S_STAT CLK_APB1_CAN1_CFG CLK_APB1_CAN1_STAT - CLK_SPIFI_CFG CLK_SPIFI_STAT - CLK_M3_BUS_CFG CLK_M3_BUS_STAT ...
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... NXP Semiconductors Table 78. Register overview: CCU1 (base address 0x4005 1000) Name CLK_M3_GPIO_CFG CLK_M3_GPIO_STAT CLK_M3_LCD_CFG CLK_M3_LCD_STAT CLK_M3_ETHERNET_CFG CLK_M3_ETHERNET_STAT CLK_M3_USB0_CFG CLK_M3_USB0_STAT CLK_M3_EMC_CFG CLK_M3_EMC_STAT CLK_M3_SDIO_CFG CLK_M3_SDIO_STAT CLK_M3_DMA_CFG CLK_M3_DMA_STAT CLK_M3_M3CORE_CFG CLK_M3_M3CORE_STAT - CLK_M3_AES_CFG CLK_M3_AES_STAT CLK_M3_SCT_CFG CLK_M3_SCT_STAT CLK_M3_USB1_CFG CLK_M3_USB1_STAT CLK_M3_EMCDIV_CFG CLK_M3_EMCDIV_STAT - CLK_M3_WWDT_CFG CLK_M3_WWDT_STAT CLK_M3_USART0_CFG CLK_M3_USART0_STAT CLK_M3_UART1_CFG CLK_M3_UART1_STAT ...
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... NXP Semiconductors Table 78. Register overview: CCU1 (base address 0x4005 1000) Name CLK_M3_SCU_STAT CLK_M3_CREG_CFG CLK_M3_CREG_STAT - CLK_M3_RITIMER_CFG CLK_M3_RITIMER_STAT CLK_M3_USART2_CFG CLK_M3_USART2_STAT CLK_M3_USART3_CFG CLK_M3_USART3_STAT CLK_M3_TIMER2_CFG CLK_M3_TIMER2_STAT CLK_M3_TIMER3_CFG CLK_M3_TIMER3_STAT CLK_M3_SSP1_CFG CLK_M3_SSP1_STAT CLK_M3_QEI_CFG CLK_M3_QEI_STAT - - CLK_USB0_CFG CLK_USB0_STAT - CLK_USB1_CFG CLK_USB1_STAT - CLK_VADC_CFG CLK_VADC_STAT Table 79. Register overview: CCU2 (base address 0x4005 2000) ...
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... NXP Semiconductors Table 79. Register overview: CCU2 (base address 0x4005 2000) Name Access CLK_APLL_STAT CLK_APB2_USART3_CFG R/W CLK_APB2_USART3_STAT CLK_APB2_USART2_CFG R/W CLK_APB2_USART2_STAT CLK_APB0_UART1_CFG R/W CLK_APB0_UART1_STAT CLK_APB0_USART0_CFG R/W CLK_APB0_USART0_STAT CLK_APB2_SSP1_CFG R/W CLK_APB2_SSP1_STAT CLK_APB0_SSP0_CFG R/W CLK_APB0_SSP0_STAT CLK_SDIO_CFG R/W CLK_SDIO_STAT R 10.5.1 Power mode register This register contains a single bit, PD, that when set will disable all output clocks with Wake-up enabled (i ...
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... NXP Semiconductors Table 80. CCU1/2 power mode register (CCU1_PM, address 0x4005 1000 and CCU2_PM, address 0x4005 2000) bit description Bit Symbol 0 PD 31:1 - 10.5.2 Base clock status register Each bit in this register indicates if the specified base clock can be safely switched off. A logic zero indicates that all branch clocks generated from this base clock are disabled. ...
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... NXP Semiconductors Table 82. CCU2 base clock status register (CCU2_BASE_STAT, address 0x4005 2004) bit description Bit Symbol BASE_UART3_ CLK 2 BASE_UART2_ CLK 3 BASE_UART1_ CLK 4 BASE_UART0_ CLK 5 BASE_SSP1_ CLK 6 BASE_SSP0_ CLK 7 - 31:8 - 10.5.3 CCU1/2 branch clock configuration registers Each generated output clock from the CCU has a configuration register. They all follow the format as described in On the LPC18xx, all branch clocks are in Run mode after reset ...
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... NXP Semiconductors Remark: In order to safely disable any of the branch clocks, use two separate writes to the CLK_XXX_CFG register: first set the AUTO bit, and then on the next write, disable the clock by setting the RUN bit to zero. Table 83. CCU1 branch clock configuration register (CLK_XXX_CFG, addresses 0x4005 1100, 0x4005 1104, ...
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... NXP Semiconductors Table 85. CCU2 branch clock configuration register (CLK_XXX_CFG, addresses 0x4005 2100, 0x4005 2200,..., 0x4005 2800) bit description Bit Symbol 0 RUN 1 AUTO 2 WAKEUP 31:3 - 10.5.4 CCU1/2 branch clock status registers Like the Configuration Register, each generated output clock from the CCU has a status register ...
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... NXP Semiconductors Table 87. CCU2 branch clock status register (CLK_XXX_STAT, addresses 0x4005 2104, 0x4005 2204,..., 0x4005 2804) bit description Bit Symbol 0 RUN 1 AUTO 2 WAKEUP 31:3 - 10.6 Functional description <tbd> <Document ID> User manual Chapter 10: LPC18xx Clock Control Unit (CCU) Description Run enable status ...
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UM10430 Chapter 11: LPC18xx Reset Generation Unit (RGU) Rev. 00.13 — 20 July 2011 11.1 How to read this chapter The C_CAN1 reset (#54) is available on parts LPC1850_30_20_10 Rev ‘A’ only. 11.2 Basic configuration Table 88. RGU clocking and ...
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... NXP Semiconductors Table 89. Reset output configuration Reset output generator CORE_RST PERIPH_RST MASTER_RST Reserved WWDT_RST CREG_RST Reserved BUS_RST SCU_RST Reserved M3_RST Reserved Reserved LCD_RST USB0_RST USB1_RST DMA_RST SDIO_RST EMC_RST ETHERNET_RST AES_RST Reserved GPIO_RST Reserved TIMER0_RST TIMER1_RST TIMER2_RST TIMER3_RST RITIMER_RST SCT_RST MOTOCONPWM_RST 38 QEI_RST < ...
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... NXP Semiconductors Table 89. Reset output configuration Reset output generator ADC0_RST ADC1_RST DAC_RST Reserved UART0_RST UART1_RST UART2_RST UART3_RST I2C0_RST I2C1_RST SSP0_RST SSP1_RST I2S_RST SPIFI_RST CAN1_RST CAN0_RST Reserved Reserved Reserved The RGU also monitors the reset cause for each reset output. The reset cause can be retrieved with two levels of granularity ...
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... NXP Semiconductors BOD reset signal • WWDT time-out signal • 11.3.1 Reset hierarchy The hierarchy is as follows (see 1. External reset, BOD reset signal, WWDT time-out, and reset signal from the PMU 2. CORE_RST (inputs are the external reset pin, BOD reset, and the WWDT time-out reset) ...
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... NXP Semiconductors 11.4 Register overview Table 91. Register overview: RGU (base address: 0x4005 3000) Name Access RESET_CTRL0 W RESET_CTRL1 W RESET_STATUS0 R/W RESET_STATUS1 R/W RESET_STATUS2 R/W RESET_STATUS3 R/W RESET_ACTIVE_STATUS0 R RESET_ACTIVE_STATUS1 R RESET_EXT_STAT0 R/W RESET_EXT_STAT1 R/W RESET_EXT_STAT2 R/W RESET_EXT_STAT3 - RESET_EXT_STAT4 R/W RESET_EXT_STAT5 R/W RESET_EXT_STAT6 - RESET_EXT_STAT7 - RESET_EXT_STAT8 ...
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... NXP Semiconductors Table 91. Register overview: RGU (base address: 0x4005 3000) Name Access RESET_EXT_STAT20 R/W RESET_EXT_STAT21 R/W RESET_EXT_STAT22 R/W RESET_EXT_STAT23 R/W RESET_EXT_STAT24 - RESET_EXT_STAT25 - RESET_EXT_STAT26 - RESET_EXT_STAT27 - RESET_EXT_STAT28 R/W RESET_EXT_STAT29 - RESET_EXT_STAT30 - RESET_EXT_STAT31 - RESET_EXT_STAT32 R/W RESET_EXT_STAT33 R/W RESET_EXT_STAT34 R/W RESET_EXT_STAT35 R/W RESET_EXT_STAT36 R/W RESET_EXT_STAT37 R/W ...
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... NXP Semiconductors Table 91. Register overview: RGU (base address: 0x4005 3000) Name Access RESET_EXT_STAT46 R/W RESET_EXT_STAT47 R/W RESET_EXT_STAT48 R/W RESET_EXT_STAT49 R/W RESET_EXT_STAT50 R/W RESET_EXT_STAT51 R/W RESET_EXT_STAT52 R/W RESET_EXT_STAT53 R/W RESET_EXT_STAT54 R/W RESET_EXT_STAT55 R/W RESET_EXT_STAT56 - RESET_EXT_STAT57 - RESET_EXT_STAT58 - RESET_EXT_STAT59 - RESET_EXT_STAT60 - RESET_EXT_STAT61 - RESET_EXT_STAT62 - RESET_EXT_STAT63 - 11.4.1 RGU reset control register The RGU reset control register allows software to activate and clear individual reset outputs ...
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... NXP Semiconductors Table 92. Reset control register 0 (RESET_CTRL0, address 0x4005 3100) bit description Bit Symbol Description 0 CORE_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. 1 PERIPH_RST Writing a one activates the reset. This bit is automatically cleared to 0 after three clock cycles. ...
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... NXP Semiconductors Table 92. Reset control register 0 (RESET_CTRL0, address 0x4005 3100) bit description Bit Symbol Description 28 GPIO_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle Reserved 30 - Reserved 31 - Reserved Table 93. Reset control register 1 (RESET_CTRL1, address 0x4005 3104) bit description ...
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... NXP Semiconductors Table 93. Reset control register 1 (RESET_CTRL1, address 0x4005 3104) bit description …continued Bit Symbol 18 SSP0_RST 19 SSP1_RST 20 I2S_RST 21 SPIFI_RST 22 CAN1_RST 23 CAN0_RST 11.4.2 RGU reset status register The reset status register shows which source (if any) caused the last reset activation per individual reset output of the RGU. When one (or more) inputs of the RGU caused the ...
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... NXP Semiconductors Table 94. Reset status register 0 (RESET_STATUS0, address 0x4005 3110) bit description Bit Symbol Description 1:0 CORE_RST Status of the CORE_RST reset generator output reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 3:2 ...
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... NXP Semiconductors Table 94. Reset status register 0 (RESET_STATUS0, address 0x4005 3110) bit description Bit Symbol Description 27:26 M3_RST Status of the M3_RST reset generator output reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register 29:28 ...
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... NXP Semiconductors Table 95. Reset status register 1 (RESET_STATUS1, address 0x4005 3114) bit description …continued Bit Symbol Description 13:12 ETHERNET_RST Status of the ETHERNET_RST reset generator output reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register ...
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... NXP Semiconductors Table 96. Reset status register 2 (RESET_STATUS2, address 0x4005 3118) bit description …continued Bit Symbol Description 7:6 TIMER3_RST Status of the TIMER3_RST reset generator output reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register ...
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... NXP Semiconductors Table 96. Reset status register 2 (RESET_STATUS2, address 0x4005 3118) bit description …continued Bit Symbol Description 25:24 UART0_RST Status of the UART0_RST reset generator output reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register ...
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... NXP Semiconductors Table 97. Reset status register 3 (RESET_STATUS3, address 0x4005 311C) bit description …continued Bit Symbol Description 7:6 SSP1_RST Status of the SSP1_RST reset generator output reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register ...
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... NXP Semiconductors Table 98. Reset active status register 0 (RESET_ACTIVE_STATUS0, address 0x4005 3150) bit description Bit Symbol 0 CORE_RST 1 PERIPH_RST 2 MASTER_RST WWDT_RST 5 CREG_RST BUS_RST 9 SCU_RST 10 PINMUX_RST M3_RST LCD_RST 17 USB0_RST <Document ID> User manual Chapter 11: LPC18xx Reset Generation Unit (RGU) Description Current status of the CORE_RST ...
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... NXP Semiconductors Table 98. Reset active status register 0 (RESET_ACTIVE_STATUS0, address 0x4005 3150) bit description Bit Symbol 18 USB1_RST 19 DMA_RST 20 SDIO_RST 21 EMC_RST 22 ETHERNET_RST 23 AES_RST GPIO_RST <Document ID> User manual Chapter 11: LPC18xx Reset Generation Unit (RGU) …continued Description Current status of the USB1_RST 0 = Reset asserted reset ...
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... NXP Semiconductors Table 99. Reset active status register 1 (RESET_ACTIVE_STATUS1, address 0x4005 3154) bit description Bit Symbol 0 TIMER0_RST 1 TIMER1_RST 2 TIMER2_RST 3 TIMER3_RST 4 RITIMER_RST 5 SCT_RST 6 MOTOCONPWM_RST 7 QEI_RST 8 ADC0_RST 9 ADC1_RST 10 DAC_RST UART0_RST 13 UART1_RST <Document ID> User manual Chapter 11: LPC18xx Reset Generation Unit (RGU) Description Current status of the TIMER0_RST ...
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... NXP Semiconductors Table 99. Reset active status register 1 (RESET_ACTIVE_STATUS1, address 0x4005 3154) bit description Bit Symbol 14 UART2_RST 15 UART3_RST 16 I2C0_RST 17 I2C1_RST 18 SSP0_RST 19 SSP1_RST 20 I2S_RST 21 SPIFI_RST 22 CAN1_RST 23 CAN0_RST <Document ID> User manual Chapter 11: LPC18xx Reset Generation Unit (RGU) …continued Description Current status of the UART2_RST ...
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... NXP Semiconductors 11.4.4 Reset external status registers The external status registers indicate which input to the reset generator caused the reset output to go active. Any bit set the Reset external status register should be cleared to 0 after a read operation to allow the detection of the next reset. ...
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... NXP Semiconductors Table 101. Reset external status register 1 (RESET_EXT_STAT1, address 0x4005 3404) bit description Bit Symbol CORE_RESET Reset activated by CORE_RST output. Write 0 to 31:2 - 11.4.4.3 Reset external status register 2 for MASTER_RST Table 102. Reset external status register 2 (RESET_EXT_STAT2, address 0x4005 3408) bit ...
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... NXP Semiconductors 11.4.4.6 Reset external status registers for PERIPHERAL_RESET Refer to Table 91 source. Table 105. Reset external status registers x (RESET_EXT_STATx, address 0x4005 34xx) bit description Bit Symbol 1 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST 31:3 - 11.4.4.7 Reset external status registers for MASTER_RESET Refer to Table 91 source. These are the ARM Cortex-M3 core, the LCD controller, the USB0, the GPDMA, the SDIO controller, the external memory controller, the Ethernet controller, and the AES ...
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UM10430 Chapter 12: LPC18xx Pin configuration Rev. 00.13 — 20 July 2011 12.1 How to read this chapter This chapter applies to parts LPC1850_30_20_10 Rev ‘A’ only. 12.2 Pin description On the LPC18xx, digital pins are grouped into 16 ports, ...
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... NXP Semiconductors Table 107. Pin description Symbol Multiplexed digital pins P0_0 P0_1 P1_0 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ I/O GPIO0[0] — General purpose digital input/output pin. I/O SSP1_MISO — Master In Slave Out for SSP1. ...
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... NXP Semiconductors Table 107. Pin description …continued Symbol P1_1 P1_2 P1_3 P1_4 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ I/O GPIO0[8] — General purpose digital input/output pin. Boot pin (see O CTOUT_7 — SCT output 7. Match output 3 of timer 1. ...
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... NXP Semiconductors Table 107. Pin description …continued Symbol P1_5 P1_6 P1_7 P1_8 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ I/O GPIO1[8] — General purpose digital input/output pin. O CTOUT_10 — SCT output 10. Match output 2 of timer — Function reserved. ...
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... NXP Semiconductors Table 107. Pin description …continued Symbol P1_9 P1_10 P1_11 P1_12 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ I/O GPIO1[2] — General purpose digital input/output pin. O U1_RTS — Request to Send output for UART1. O CTOUT_11 — SCT output 11. Match output 3 of timer 2. ...
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... NXP Semiconductors Table 107. Pin description …continued Symbol P1_13 R10 P1_14 R11 P1_15 T12 P1_16 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ I/O GPIO1[6] — General purpose digital input/output pin. O U1_TXD — Transmitter output for UART1. ...
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... NXP Semiconductors Table 107. Pin description …continued Symbol P1_17 P1_18 N12 P1_19 M11 P1_20 M10 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ I/O GPIO0[12] — General purpose digital input/output pin. I/O U2_UCLK — Serial clock input/output for USART2 in synchronous mode ...
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... NXP Semiconductors Table 107. Pin description …continued Symbol P2_0 T16 P2_1 N15 P2_2 M15 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ — Function reserved. O U0_TXD — Transmitter output for USART0. I/O EMC_A13 — External memory address line 13. ...
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... NXP Semiconductors Table 107. Pin description …continued Symbol P2_3 J12 P2_4 K11 P2_5 K14 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ — Function reserved. I/O I2C1_SDA — I use a specialized I O U3_TXD — Transmitter output for USART3. ...
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... NXP Semiconductors Table 107. Pin description …continued Symbol P2_6 K16 P2_7 H14 P2_8 J16 P2_9 H16 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ — Function reserved. I/O U0_DIR — RS-485/EIA-485 output enable/direction control for USART0. I/O EMC_A10 — ...
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... NXP Semiconductors Table 107. Pin description …continued Symbol P2_10 G16 P2_11 F16 P2_12 E15 P2_13 C16 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [3] 104 I; PU I/O GPIO0[14] — General purpose digital input/output pin. O CTOUT_2 — SCT output 2. Match output 2 of timer 0. ...
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... NXP Semiconductors Table 107. Pin description …continued Symbol P3_0 F13 P3_1 G11 P3_2 F11 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [3] 112 I; PU I/O I2S0_RX_SCK — I2S transmit clock driven by the master and received by the slave. Corresponds to the ...
Page 146
... NXP Semiconductors Table 107. Pin description …continued Symbol P3_3 B14 P3_4 A15 P3_5 C12 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [5] 118 — Function reserved — Function reserved. I/O SSP0_SCK — Serial clock for SSP0. ...
Page 147
... NXP Semiconductors Table 107. Pin description …continued Symbol P3_6 B13 P3_7 C11 P3_8 C10 P4_0 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [3] 122 I; PU I/O GPIO0[6] — General purpose digital input/output pin — Function reserved. ...
Page 148
... NXP Semiconductors Table 107. Pin description …continued Symbol P4_1 P4_2 P4_3 P4_4 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ I/O GPIO2[1] — General purpose digital input/output pin. O CTOUT_1 — SCT output 1. Match output 1 of timer 0. O LCD_VD0 — LCD data. ...
Page 149
... NXP Semiconductors Table 107. Pin description …continued Symbol P4_5 P4_6 P4_7 P4_8 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ I/O GPIO2[5] — General purpose digital input/output pin. O CTOUT_5 — SCT output 5. Match output 1 of timer 1. O LCD_FP — Frame pulse (STN). Vertical synchronization pulse (TFT) ...
Page 150
... NXP Semiconductors Table 107. Pin description …continued Symbol P4_9 P4_10 P5_0 P5_1 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ — Function reserved. I CTIN_6 — SCT input 6. Capture input 1 of timer 3. O LCD_VD11 — LCD data — Function reserved. ...
Page 151
... NXP Semiconductors Table 107. Pin description …continued Symbol P5_2 P5_3 P5_4 P5_5 P10 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ I/O GPIO2[11] — General purpose digital input/output pin. I MCI1 — Motor control PWM channel 1, input. I/O EMC_D14 — ...
Page 152
... NXP Semiconductors Table 107. Pin description …continued Symbol P5_6 T13 P5_7 R12 P6_0 M12 P6_1 R15 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ I/O GPIO2[15] — General purpose digital input/output pin. O MCOB1 — Motor control PWM channel 1, output B. ...
Page 153
... NXP Semiconductors Table 107. Pin description …continued Symbol P6_2 L13 P6_3 P15 P6_4 R16 P6_5 P16 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ I/O GPIO3[1] — General purpose digital input/output pin. O EMC_CKEOUT1 — SDRAM clock enable 1. ...
Page 154
... NXP Semiconductors Table 107. Pin description …continued Symbol P6_6 L14 P6_7 J13 P6_8 H13 P6_9 J15 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ I/O GPIO0[5] — General purpose digital input/output pin. O EMC_BLS1 — LOW active Byte Lane select signal 1. ...
Page 155
... NXP Semiconductors Table 107. Pin description …continued Symbol P6_10 H15 P6_11 H12 P6_12 G15 P7_0 B16 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [3] 100 I; PU I/O GPIO3[6] — General purpose digital input/output pin. O MCABORT — Motor control PWM, LOW-active fast abort ...
Page 156
... NXP Semiconductors Table 107. Pin description …continued Symbol P7_1 C14 P7_2 A16 P7_3 C13 P7_4 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [3] 113 I; PU I/O GPIO3[9] — General purpose digital input/output pin. O CTOUT_15 — SCT output 15. Match output 3 of timer 3. ...
Page 157
... NXP Semiconductors Table 107. Pin description …continued Symbol P7_5 P7_6 P7_7 P8_0 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [6] 133 I; PU I/O GPIO3[13] — General purpose digital input/output pin. O CTOUT_12 — SCT output 12. Match output 0 of timer 3. ...
Page 158
... NXP Semiconductors Table 107. Pin description …continued Symbol P8_1 P8_2 P8_3 P8_4 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ I/O GPIO4[1] — General purpose digital input/output pin. O USB0_IND1 — USB0 port indicator LED control output — Function reserved. ...
Page 159
... NXP Semiconductors Table 107. Pin description …continued Symbol P8_5 P8_6 P8_7 P8_8 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ I/O GPIO4[5] — General purpose digital input/output pin. I/O USB1_ULPI_D0 — ULPI link bidirectional data line — Function reserved. ...
Page 160
... NXP Semiconductors Table 107. Pin description …continued Symbol P9_0 P9_1 P9_2 P9_3 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ I/O GPIO4[12] — General purpose digital input/output pin. O MCABORT — Motor control PWM, LOW-active fast abort — Function reserved. ...
Page 161
... NXP Semiconductors Table 107. Pin description …continued Symbol P9_4 N10 P9_5 P9_6 L11 PA_0 L12 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ — Function reserved. O MCOB0 — Motor control PWM channel 0, output B. O USB1_IND0 — USB1 Port indicator LED control output ...
Page 162
... NXP Semiconductors Table 107. Pin description …continued Symbol PA_1 J14 PA_2 K15 PA_3 H11 PA_4 G13 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ I/O GPIO4[8] — General purpose digital input/output pin. I QEI_IDX — Quadrature Encoder Interface INDEX input. ...
Page 163
... NXP Semiconductors Table 107. Pin description …continued Symbol PB_0 B15 PB_1 A14 PB_2 B12 PB_3 A13 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ — Function reserved. O CTOUT_10 — SCT output 10. Match output 2 of timer 2. O LCD_VD23 — LCD data. ...
Page 164
... NXP Semiconductors Table 107. Pin description …continued Symbol PB_4 B11 PB_5 A12 PB_6 PC_0 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ — Function reserved. I/O USB1_ULPI_D5 — ULPI link bidirectional data line 5. O LCD_VD15 — LCD data. ...
Page 165
... NXP Semiconductors Table 107. Pin description …continued Symbol PC_1 PC_2 PC_3 PC_4 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ I/O USB1_ULPI_D7 — ULPI link bidirectional data line — Function reserved. I U1_RI — Ring Indicator input for UART 1. ...
Page 166
... NXP Semiconductors Table 107. Pin description …continued Symbol PC_5 PC_6 PC_7 PC_8 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ — Function reserved. I/O USB1_ULPI_D3 — ULPI link bidirectional data line — Function reserved. O ENET_TX_ER — Ethernet Transmit Error (MII interface). ...
Page 167
... NXP Semiconductors Table 107. Pin description …continued Symbol PC_9 PC_10 PC_11 PC_12 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ — Function reserved. I USB1_ULPI_NXT — ULPI link NXT signal. Data flow control signal from the PHY — Function reserved. ...
Page 168
... NXP Semiconductors Table 107. Pin description …continued Symbol PC_13 PC_14 PD_0 PD_1 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ — Function reserved — Function reserved. O U1_TXD — Transmitter output for UART — Function reserved. I/O GPIO6[12] — General purpose digital input/output pin. ...
Page 169
... NXP Semiconductors Table 107. Pin description …continued Symbol PD_2 PD_3 PD_4 PD_5 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ — Function reserved. O CTOUT_7 — SCT output 7. Match output 3 of timer 1. I/O EMC_D16 — External memory data line 16. ...
Page 170
... NXP Semiconductors Table 107. Pin description …continued Symbol PD_6 PD_7 PD_8 PD_9 T11 - - x <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ — Function reserved. O CTOUT_10 — SCT output 10. Match output 2 of timer 2. I/O EMC_D20 — External memory data line 20. ...
Page 171
... NXP Semiconductors Table 107. Pin description …continued Symbol PD_10 P11 - - x PD_11 PD_12 N11 PD_13 T14 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ — Function reserved. I CTIN_1 — SCT input 1. Capture input 1 of timer 0. Capture input 1 of timer 2 ...
Page 172
... NXP Semiconductors Table 107. Pin description …continued Symbol PD_14 R13 PD_15 T15 PD_16 R14 PE_0 P14 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ — Function reserved — Function reserved. O EMC_DYCS2 — SDRAM chip select — Function reserved. ...
Page 173
... NXP Semiconductors Table 107. Pin description …continued Symbol PE_1 N14 PE_2 M14 PE_3 K12 PE_4 K13 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ — Function reserved — Function reserved — Function reserved. I/O EMC_A19 — External memory address line 19. ...
Page 174
... NXP Semiconductors Table 107. Pin description …continued Symbol PE_5 N16 - - x PE_6 M16 - - x PE_7 F15 - - x PE_8 F14 - - x <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ — Function reserved. O CTOUT_3 — SCT output 3. Match output 3 of timer 0. O U1_RTS — Request to Send output for UART 1. Can also be configured RS-485/EIA-485 output enable signal for UART 1 ...
Page 175
... NXP Semiconductors Table 107. Pin description …continued Symbol PE_9 E16 - - x PE_10 E14 - - x PE_11 D16 - - - PE_12 D15 - - - <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ — Function reserved. I CTIN_4 — SCT input 4. Capture input 2 of timer 1. I U1_DCD — Data Carrier Detect input for UART 1. ...
Page 176
... NXP Semiconductors Table 107. Pin description …continued Symbol PE_13 G14 - - - PE_14 C15 - - - PE_15 E13 - - - PF_0 D12 - - - <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ — Function reserved. O CTOUT_14 — SCT output 14. Match output 2 of timer 3. I/O I2C1_SDA — I ...
Page 177
... NXP Semiconductors Table 107. Pin description …continued Symbol PF_1 E11 - - - PF_2 D11 - - x PF_3 E10 - - x PF_4 D10 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ — Function reserved — Function reserved. I/O SSP0_SSEL — Slave Select for SSP0. ...
Page 178
... NXP Semiconductors Table 107. Pin description …continued Symbol PF_5 PF_6 PF_7 <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ — Function reserved. I/O U3_UCLK — Serial clock input/output for USART3 in synchronous mode. I/O SSP1_SSEL — Slave Select for SSP1. ...
Page 179
... NXP Semiconductors Table 107. Pin description …continued Symbol PF_8 PF_9 PF_10 PF_11 Clock pins <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ — Function reserved. I/O U0_UCLK — Serial clock input/output for USART0 in synchronous mode. I CTIN_2 — SCT input 2. Capture input 2 of timer 0. ...
Page 180
... NXP Semiconductors Table 107. Pin description …continued Symbol CLK0 CLK1 T10 CLK2 D14 CLK3 P12 Debug pins <Document ID> User manual Chapter 12: LPC18xx Pin configuration Reset Type Description state [2] [ EMC_CLK0 — SDRAM clock 0. O CLKOUT — Clock output pin — Function reserved. ...
Page 181
... NXP Semiconductors Table 107. Pin description …continued Symbol DBGEN TCK/SWDCLK TRST TMS/SWDIO TDO/SWO TDI USB0 pins USB0_DP USB0_DM USB0_VBUS USB0_ID USB0_RREF USB1 pins USB1_DP F12 USB1_DM G12 C-bus pins I2C0_SCL L15 I2C0_SDA L16 Reset and wake-up pins RESET WAKEUP0 WAKEUP1 A10 ...
Page 182
... NXP Semiconductors Table 107. Pin description …continued Symbol ADC0_1 ADC1_1 ADC0_2 ADC1_2 ADC0_3 ADC1_3 ADC0_4 ADC1_4 ADC0_5 ADC1_5 ADC0_6 ADC1_6 ADC0_7 ADC1_7 RTC RTC_ALARM A11 RTCX1 RTCX2 Crystal oscillator pins XTAL1 XTAL2 Power and ground pins USB0_VDDA 3V3_DRIVER USB0 _VDDA3V3 USB0_VSSA ...
Page 183
... NXP Semiconductors Table 107. Pin description …continued Symbol VDDIO D7 E12, F7, F8, G10, H10, J6, J7, K7, L9, L10, N7, N13 VSS G9 H7, J10, J11, K8 VSSIO C4 D13, G6, G7, G8, H8, H9, J8, J9, K9, K10, M13, P7, P13 VSSA Not connected - B9 [ available not pinned out. [ input output inactive pull-up enabled (weak pull-up resistor pulls up pin tolerant pad with 15 ns glitch filter ...
Page 184
... NXP Semiconductors [10] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. This pad requires an external pull-up to provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. ...
Page 185
UM10430 Chapter 13: LPC18xx System Control Unit (SCU) Rev. 00.13 — 20 July 2011 13.1 How to read this chapter Remark: This chapter describes parts LPC1850/30/20/10 Rev ‘A’ and parts LPC18xx (with on-chip flash). For a description of the SCU ...
Page 186
... NXP Semiconductors The possible on-chip resistor configurations are pull-up enabled, pull-down enabled pull-up/pull-down. The default value is pull-up enabled. The repeater mode enables the pull-up resistor if the pin logic HIGH and enables the pull-down resistor if the pin logic LOW. This causes the pin to retain its last known state configured as an input and is not driven externally ...
Page 187
Pin multiplexing Table 109. Pin multiplexing Function level 0 1 P0_0 GPIO0[0] SSP1_ MISO P0_1 ...
Page 188
Table 109. Pin multiplexing Function level 0 1 P1_15 T12 GPIO0[2] U2_TXD P1_16 GPIO0[3] U2_RXD P1_17 ...
Page 189
Table 109. Pin multiplexing Function level 0 1 P2_9 H16 102 GPIO1[10] CTOUT_3 P2_10 G16 104 GPIO0[14] CTOUT_2 P2_11 ...
Page 190
Table 109. Pin multiplexing Function level 0 1 P4_4 GPIO2[4] CTOUT_2 P4_5 GPIO2[5] CTOUT_5 P4_6 ...
Page 191
Table 109. Pin multiplexing Function level 0 1 P6_5 P16 GPIO3[4] CTOUT_6 P6_6 L14 GPIO0[5] EMC_ BLS1 ...
Page 192
Table 109. Pin multiplexing Function level 0 1 P8_0 GPIO4[0] USB0_ PWR_ FAULT P8_1 GPIO4[1] ...
Page 193
Table 109. Pin multiplexing Function level 0 1 P9_6 L11 GPIO4[11] MCOB1 PA_0 L12 PA_1 ...
Page 194
Table 109. Pin multiplexing Function level 0 1 PC_4 USB1_ ULPI_D4 PC_5 USB1_ ...
Page 195
Table 109. Pin multiplexing Function level 0 1 PD_7 CTIN_5 PD_8 CTIN_6 PD_9 ...
Page 196
Table 109. Pin multiplexing Function level 0 1 PE_14 C15 - - - - R R PE_15 E13 - - - - R CTOUT_0 PF_0 ...
Page 197
Table 109. Pin multiplexing Function level 0 1 CLK0 EMC_CLK CLKOUT 0 CLK1 T10 EMC_ CLKOUT ...
Page 198
Register description Table 110. Register overview: System Control Unit (SCU) (base address 0x4008 6000) Name Access Pins P0_n SFSP0_0 R/W SFSP0_1 R ...
Page 199
... NXP Semiconductors Table 110. Register overview: System Control Unit (SCU) (base address 0x4008 6000) …continued Name - Pins P2_n SFSP2_0 SFSP2_1 SFSP2_2 SFSP2_3 SFSP2_4 SFSP2_5 SFSP2_6 SFSP2_7 SFSP2_8 SFSP2_9 SFSP2_10 SFSP2_11 SFSP2_12 SFSP2_13 - Pins P3_n SFSP3_0 SFSP3_1 SFSP3_2 SFSP3_3 SFSP3_4 SFSP3_5 SFSP3_6 ...
Page 200
... NXP Semiconductors Table 110. Register overview: System Control Unit (SCU) (base address 0x4008 6000) …continued Name SFSP4_8 SFSP4_9 SFSP4_10 - Pins P5_n SFSP5_0 SFSP5_1 SFSP5_2 SFSP5_3 SFSP5_4 SFSP5_5 SFSP5_6 SFSP5_7 - Pins P6_n SFSP6_0 SFSP6_1 SFSP6_2 SFSP6_3 SFSP6_4 SFSP6_5 SFSP6_6 SFSP6_7 SFSP6_8 SFSP6_9 ...