LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 44

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
LPC1850_30_20_10
Objective data sheet
7.13.2.1 Features
7.13.3.1 Features
7.13.3 SSP0/1 serial I/O controllers
7.13.4 I
The LPC1850/30/20/10 contain two SSP controllers. The SSP controller is capable of
operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and
slaves on the bus. Only a single master and a single slave can communicate on the bus
during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits
to 16 bits of data flowing from the master to the slave and from the slave to the master. In
practice, often only one of these data flows carries meaningful data.
The LPC1850/30/20/10 each contain two I
The I
(SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
controlled by more than one bus master connected to it.
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C0/1-bus interfaces
Maximum UART data bit rate of <tbd> MBit/s.
16 B Receive and Transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
Auto baud capabilities and FIFO control mechanism that enables software flow
control implementation.
Support for RS-485/9-bit/EIA-485 mode.
USART3 includes an IrDA mode to support infrared communication.
All USARTs have DMA support.
Support for synchronous mode.
Smart card mode conforming to ISO7816 specification
Maximum SSP speed of <tbd> Mbit/s (master) or <tbd> Mbit/s (slave)
Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
DMA transfers supported by GPDMA
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C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 17 February 2011
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C-bus controllers.
32-bit ARM Cortex-M3 microcontroller
LPC1850/30/20/10
2
C is a multi-master bus and can be
© NXP B.V. 2011. All rights reserved.
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