MAXQ1004-B01+ Maxim Integrated Products, MAXQ1004-B01+ Datasheet - Page 14

• Manufacturer Part Number: MAXQ1004-B01+
• Description: Microcontrollers (MCU) 1-Wire and SPI Authentication MCU
• Manufacturer: Maxim Integrated Products

Specifications of MAXQ1004-B01+

• Processor Series: MAXQ1004
• Core: RISC
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 16 KB
• Data Ram Size: 640 B
• Interface Type: 1-Wire, SPI, JTAG, TAP
• Maximum Clock Frequency: 6 MHz
• Number Of Timers: 1
• Operating Supply Voltage: 1.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFN-EP-16
• Development Tools By Supplier: MAXQ1004-KIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / Rohs Status: Details

1-Wire and SPI Authentication Microcontroller
The 1-Wire slave provides three functions. The first is
that of a totally independent slave function, which can
be externally accessed at any time to verify its identity.
The 1-Wire front-end functions in an identical fashion to
that of the DS1990 serial ID to verify the serial ID number.
The bus master must provide one of the ROM function
commands:
• Read ROM
• Match ROM
• Search ROM
• Skip ROM
• Overdrive-Skip ROM
• Overdrive-Match ROM
• Resume
The second function is that of a 1-Wire that includes full
bidirectional data flow and data flow control. The 1-Wire
functions that become accessible after a ROM function
command is successfully executed initiate communica-
tions with the microcontroller through the use of specific
1-Wire commands:
• Read I/O Buffer
• Write I/O Buffer
• Read Command Buffer
• Write Command Buffer
• Read Command Buffer Extended
• Write Command Buffer Extended
• Status Register Read
• Status Register Write
The third function controls the operation of the 1-Wire
interface:
• 1-Wire Micro Reset
And the remaining are 1-Wire run commands:
• Start Program
• Continue Program
• Write Command Buffer Extended and Start Program
• Write Command Buffer Extended and Continue Program
The low-power mode of operation is stop mode. In this
mode, CPU state and memories are preserved, but the
CPU is not actively running. Wake-up sources include
external I/O interrupts, the power-fail warning interrupt,
14
Operating Modes
Slave Functionality
a valid 1-Wire command received, or a power-fail reset.
Any time the microcontroller is in a state where code
does not need to be executed, the user software can
enter stop mode.
An even lower stop mode is the data-retention mode,
in which the CPU is not active. When the data-retention
mode option is invoked (DRET = 1) and the regula-
tor is disabled (REGEN = 0), only the first 512 bytes
of data memory is retained (data memory word offset
0000h–00FFh). CPU status and 1-Wire/AES memory are
powered down and contents are lost. A POR occurs
when exiting stop mode from data-retention mode. This
mode can be exited from any of the following enabled
interrupt sources:
• Enabled external interrupts
• External reset
• Enabled PFW interrupt
• Valid 1-Wire command received
• Wake-up timer
The wake-up timer causes the device to exit stop mode
after a user-selectable time period. The power-fail moni-
tor is always on during normal operation. However, it can
be selectively disabled during stop mode using the pow-
er-fail monitor disable (PFD) bit in the PWCN register. By
default, the power-fail monitor function is enabled during
stop mode. If power-fail monitoring is disabled (PFD = 1)
during stop mode, the circuitry responsible for generat-
ing a power-fail warning or reset is shut down and neither
condition is detected. Thus, the V
does not invoke a reset state. However, in the event that
V
power-fail monitor is enabled prior to stop mode exit and
before code execution begins. If a power-fail warning
condition (V
interrupt flag is set on stop mode exit. If a power-fail con-
dition is detected (V
The 1-Wire peripheral can operate in a special mode
that draws minimal power, yet can serve as a wake-
up source to bring the device out of stop mode. If the
1-Wire peripheral is required to run in stop mode, it can
be enabled so a regular 1-Wire reset pulse briefly wakes
up the 1-Wire controller. The 1-Wire controller then deter-
mines if it was addressed. If so, the 1-Wire controller
wakes up the CPU from stop mode. If the microcontroller
is not being addressed, then stop mode continues and
the 1-Wire controller is powered down again, and the
device returns to its lowest power state. The device does
not respond to an overdrive reset pulse in stop mode.
DD
falls below the POR level, a POR is generated. The
DD
< V
PFW
DD
< V
) is then detected, the power-fail
RST
), the CPU goes into reset.
DD
< V
RST
condition