SAK-XC167CI-32F40FBB-A Infineon Technologies, SAK-XC167CI-32F40FBB-A Datasheet - Page 18

• Manufacturer Part Number: SAK-XC167CI-32F40FBB-A
• Description: Microcontrollers (MCU) 256KB FLASH 12KB RAM 2xASC 2xSSC I2C
• Manufacturer: Infineon Technologies

Specifications of SAK-XC167CI-32F40FBB-A

• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 12 KB
• Interface Type: 2xASC, 2xSSC, 1xI2C
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 103
• Number Of Timers: 11
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: PG-TQFP-144
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / Rohs Status: Details
• Other names: KX167CI32F40FBBAXT

Table 2
Sym-
bol
P20
P20.0
P20.1
P20.2
P20.4
P20.5
P20.12
Data Sheet
Pin
Num.
90
91
92
93
94
3
Pin Definitions and Functions (cont’d)
Input
Outp.
IO
O
O
I
O
I
O
Function
Port 20 is a 6-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output. The input threshold of Port 20 is selectable
(standard or special).
The following Port 20 pins also serve for alternate functions:
RD
WR/WRL
READY
ALE
EA
RSTOUT
Note: Port 20 pins may input configuration values (see EA).
External Memory Read Strobe, activated for
every external instruction or data read access.
External Memory Write Strobe.
In WR-mode this pin is activated for every
external data write access.
In WRL-mode this pin is activated for low byte
data write accesses on a 16-bit bus, and for
every data write access on an 8-bit bus.
READY Input. When the READY function is
enabled, memory cycle time waitstates can be
forced via this pin during an external access.
Address Latch Enable Output.
Can be used for latching the address into
external memory or an address latch in the
multiplexed bus modes.
External Access Enable pin.
A low-level at this pin during and after Reset
forces the XC167 to latch the configuration from
PORT0 and pin RD, and to begin instruction
execution out of external memory.
A high-level forces the XC167 to latch the
configuration from pins RD, ALE, and WR, and
to begin instruction execution out of the internal
program memory. “ROMless” versions must
have this pin tied to ‘0’.
Internal Reset Indication Output.
Is activated asynchronously with an external
hardware reset. It may also be activated
(selectable) synchronously with an internal
software or watchdog reset.
Is deactivated upon the execution of the EINIT
instruction, optionally at the end of reset, or at
any time (before EINIT) via user software.
16
General Device Information
XC167CI-32F
Derivatives
V1.1, 2006-08