M95160-WMN3TP/S STMicroelectronics, M95160-WMN3TP/S Datasheet - Page 14

• Manufacturer Part Number: M95160-WMN3TP/S
• Manufacturer: STMicroelectronics

Specifications of M95160-WMN3TP/S

• Density: 16Kb
• Interface Type: Serial (SPI)
• Organization: 2Kx8
• Access Time (max): 60ns
• Frequency (max): 5MHz
• Write Protection: Yes
• Data Retention: 40Year
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: -40C to 125C
• Supply Current: 2mA
• Operating Supply Voltage (min): 2.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Compliant

Operating features
4.5
14/50
Data protection and protocol control
Non-volatile memory devices can be used in environments that are particularly noisy, and
within applications that could experience problems if memory bytes are corrupted.
Consequently, the device features the following data protection mechanisms:
●
●
●
●
For any instruction to be accepted, and executed, Chip Select (S) must be driven high after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).
Two points need to be noted in the previous sentence:
●
●
Table 3.
Status Register bits
BP1
Write and Write Status Register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
–
–
–
The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be
configured as read-only.
The Write Protect (W) signal allows the Block Protect (BP1, BP0) bits of the Status
Register to be protected.
The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).
The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus
transaction for some other device on the SPI bus.
0
0
1
1
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Write (WRITE) instruction completion
Write-protected block size
BP0
0
1
0
1
Protected block
Whole memory
Upper quarter
Upper half
none
Doc ID 8028 Rev 10
0600h - 07FFh
0400h - 07FFh
0000h - 07FFh
M95160-x
none
Protected array addresses
M95160-x, M95080-x
0300h - 03FFh
0200h - 03FFh
0000h - 03FFh
M95080-x
none