DS26303LN-120+A3 Maxim Integrated Products, DS26303LN-120+A3 Datasheet - Page 39
DS26303LN-120+A3
Manufacturer Part Number
DS26303LN-120+A3
Description
Buffers & Line Drivers 3.3V E1/T1/J1 Short Haul Octal LIU
Manufacturer
Maxim Integrated Products
Datasheet
1.DS26303LN-120A3.pdf
(101 pages)
Specifications of DS26303LN-120+A3
Lead Free Status / Rohs Status
Details
- Current page: 39 of 101
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Excessive Zero Detect Enable Channel n (EZDEn). When this bit is reset, excessive zero detection
is disabled for LIUn. When this bit is set, excessive zero detect is enabled. Excessive zero detection is only
relevant in single-rail mode with HDB3 or B8ZS decoding.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Code Violation Detect Enable Bar Channel n (CVDEBn). If this bit is set, code violation detection is
disabled for the LIUn. If this bit is reset, code violation detection is enabled. Code violation detection is only
relevant with HDB3 decoding. Note that if the GC.CODE bit is set, this register is ignored.
CVDEB8
EZDE8
7
0
7
0
CVDEB7
EZDE7
6
0
6
0
EZDE
Excessive Zero Detect Enable Register
05h
CVDEB
Code Violation Detect Enable Bar Register
06h
CVDEB6
EZDE6
5
0
5
0
CVDEB5
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
EZDE5
39 of 101
4
0
4
0
CVDEB4
EZDE4
3
0
3
0
CVDEB3
EZDE3
2
0
2
0
CVDEB2
EZDE2
1
0
1
0
CVDEB1
EZDE1
0
0
0
0
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