DS2433 Maxim Integrated Products, DS2433 Datasheet
DS2433
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DS2433 Summary of contents
Page 1
... Directly connects to a single port pin of a microprocessor and communicates 16.3kbps Overdrive mode boosts communication speed to 142kps 8-bit family code specifies DS2433 communication requirements to reader Presence detector acknowledges when reader first applies voltage Low cost PR-35, SFN, Flip Chip or 8-pin SO surface mount package Reads and writes over a wide voltage range of 2.8V to 6.0V from -40° ...
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... DS2433 are connected in parallel to form a local network. Data is transferred serially via the 1-Wire protocol which requires only a single data lead and a ground return. The PR-35 and SOIC packages provide a compact enclosure that allows standard assembly equipment to handle the device easily for attachment to printed circuit boards or wiring ...
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... Figure 1. DS2433 BLOCK DIAGRAM 64-BIT LASERED ROM Each DS2433 contains a unique ROM code that is 64 bits long. The first eight bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits. (See Figure 3 ...
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... TA1, TA2 and E/S. The master may obtain the contents of these registers by reading the scratchpad or derive it from the target address and the amount of data to be written. As soon as the DS2433 has received these bytes correctly, it will copy the data to the requested location beginning at the target address. ...
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... MEMORY FUNCTION COMMANDS The “Memory Function Flow Chart” (Figure 7) describes the protocols necessary for accessing the memory. An example follows the flowchart. The communication between master and DS2433 takes place either at regular speed (default Overdrive Speed (OD = 1). If not explicitly set into the Overdrive Mode the DS2433 assumes regular speed ...
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... CRC generated by the DS2433. The memory address range of the DS2433 is 0000H to 01FFH. If the bus master sends a target address higher than this, the internal circuitry of the chip will set the seven most significant address bits to zero as they are shifted into the internal address register ...
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... The ending offset/data status byte is unaffected. The hardware of the DS2433 provides a means to accomplish error-free writing to the memory section. To safeguard reading data in the 1-Wire environment and to simultaneously speed up data transfers recommended to packetize data into data packets of the size of one memory page each ...
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... Figure 7. MEMORY FUNCTION FLOW CHART ...
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... Figure 7. MEMORY FUNCTION FLOW CHART (continued ...
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... MEMORY FUNCTION EXAMPLE Example: Write two data bytes to memory location 0026 and 0027. Read entire memory. MASTER MODE DATA (LSB FIRST <2 data bytes> <2 data bytes> <idle or strong pullup> Reset Pulse (480 - 960 μ s) Reset Presence Presence Pulse CCH Issue Skip ROM Command ...
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... Figure 8. HARDWARE CONFIGURATION *5k Ω is adequate for reading the DS2433. To write to a single device, a 2.2k Ω resistor and V least 4.0V is sufficient. For writing multiple DS2433s simultaneously or operation at low V should be bypassed by a low-impedance pullup to V EEPROM. Depending on the 1-Wire communication speed and the bus-load characteristics, the optimal ) value will be in the 1.5k Ω ...
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... This command allows the bus master to read the DS2433’s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can only be used if there is a single DS2433 on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result) ...
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... The Overdrive Match ROM command, followed by a 64-bit ROM sequence transmitted at Overdrive Speed, allows the bus master to address a specific DS2433 on a multidrop bus and to simultaneously set it in Overdrive Mode. Only the DS2433 that exactly matches the 64-bit ROM sequence will respond to the subsequent memory function command ...
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Figure 9. ROM FUNCTIONS FLOW CHART (first part ...
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Figure 9. ROM FUNCTIONS FLOW CHART (continued ...
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... Overdrive speed) and then transmits the Presence Pulse (t Overdrive Speed). A Reset Pulse of 480 μ longer will exit the Overdrive Mode returning the device to regular speed. If the DS2433 is in Overdrive Mode and the Reset Pulse is no longer than 80 μ s the device will remain in Overdrive Mode. READ/WRITE TIME SLOTS The definitions of write and read time slots are illustrated in Figure 11 ...
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Figure 11. READ/WRITE TIMING DIAGRAM Write-one Time Slot Write-zero Time Slot Read-data Time Slot ...
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... ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the DS2433 to determine if the ROM data has been received error-free by the bus master. The equivalent polynomial ...
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ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Range Storage Temperature Range Soldering Temperature * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated ...
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... The Copy Scratchpad takes 5ms maximum during which the voltage on the 1-Wire bus must not fall below 2.8V. 11) During the execution of the Copy Scratchpad command the DS2433 automatically erases the memory locations to be written to. No extra steps need to be taken by the bus master. ...