LFE2-12SE-5TN144C Lattice, LFE2-12SE-5TN144C Datasheet - Page 110
LFE2-12SE-5TN144C
Manufacturer Part Number
LFE2-12SE-5TN144C
Description
FPGA - Field Programmable Gate Array 12K LUTs S-Series 1.1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFE2-12E-5FN256C.pdf
(385 pages)
Specifications of LFE2-12SE-5TN144C
Number Of Macrocells
12000
Maximum Operating Frequency
320 MHz
Number Of Programmable I/os
93
Data Ram Size
226304
Delay Time
12 ns
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Package / Case
TQFP-144
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2-12SE-5TN144C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
LatticeECP2 Pin Information Summary, LFE2-50 and LFE2-70 (Cont.)
Available DDR-Interfaces per I/O
Bank
PCI Capable I/Os per Bank
1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1
DQSB + 8 DQs + 1 DM + Bank VREF1).
1
Pin Type
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
4-10
484 fpBGA
46
46
0
0
2
0
3
3
1
2
0
0
0
0
0
0
0
0
LFE2-50
LatticeECP2/M Family Data Sheet
672 fpBGA
62
68
0
0
3
3
4
4
4
3
0
0
0
0
0
0
0
0
672 fpBGA
Pinout Information
62
68
0
0
3
3
4
4
4
3
0
0
0
0
0
0
0
0
LFE2-70
900 fpBGA
72
80
0
0
4
3
4
5
4
4
0
0
0
0
0
0
0
0
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