LAN8710A-EZK SMSC, LAN8710A-EZK Datasheet - Page 16

• Manufacturer Part Number: LAN8710A-EZK
• Description: TXRX ETHERNET 10/100 MII/RMII
• Manufacturer: SMSC
• Type: Transceiverr

Specifications of LAN8710A-EZK

• Number Of Drivers/receivers: 4/4
• Protocol: MII, RMII
• Voltage - Supply: 1.6 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1079; LAN8710A-EZK

Revision 1.0 (04-15-09)
3.2
REGOFF
SIGNAL
CRS_DV/
PHYAD0
PHYAD1
SIGNAL
NAME
RXCLK/
MODE2
LED1/
RXER/
NAME
RXD4/
RXDV
COL/
CRS
LED Signals
32-QFN
32-QFN
PIN #
PIN #
3
13
26
15
14
7
Table 3.2 MII/RMII Signals (continued) 32-QFN (continued)
TYPE
IOPD
TYPE
IOPD
IOPD
IOPU
IOPD
O8
LED1 – Link activity LED Indication.
See
REGOFF – Regulator Off: This pin may be used to configure the internal
1.2V regulator off. As described in
power-on sequence to determine if the internal regulator should turn on.
When the regulator is disabled, external 1.2V must be supplied to VDDCR.
RXER – Receive Error: Asserted to indicate that an error was detected
somewhere in the frame presently being transferred from the transceiver.
RXD4 – MII Receive Data 4: In Symbol Interface (5B Decoding) mode, this
signal is the MII Receive Data 4 signal, the MSB of the received 5-bit
symbol code-group. Unless configured in this mode, the pin functions as
RXER.
PHYAD0 – PHY Address Bit 0: set the SMI address of the PHY.
RXCLK – Receive Clock: In MII mode, this pin is the receive clock output.
25MHz in 100Base-TX mode. 2.5MHz in 10Base-T mode.
PHYAD1 – PHY Address Bit 1: set the SMI address of the transceiver.
Receive Data Valid: Indicates that recovered and decoded data is being
presented on RXD pins.
COL – MII Mode Collision Detect: Asserted to indicate detection of
collision condition.
CRS_DV – RMII Mode CRS_DV (Carrier Sense/Receive Data Valid)
Asserted to indicate when the receive medium is non-idle. When a 10BT
packet is received, CRS_DV is asserted, but RXD[1:0] is held low until the
SFD byte (10101011) is received. In 10BT, half-duplex mode, transmitted
data is not looped back onto the receive data pins, per the RMII standard.
MODE2 – PHY Operating Mode Bit 2: set the default MODE of the PHY.
Carrier Sense: Indicates detection of carrier.
When LED1/REGOFF is pulled high to VDD2A with an external resistor, the
internal regulator is disabled.
When LED1/REGOFF is floating or pulled low, the internal regulator is
enabled (default).
The RXER signal is optional in RMII Mode.
This signal is mux’d with PHYAD0
See
This signal is mux’d with PHYAD1
See
See
Table 3.3 LED Signals 32-QFN
Section 5.3.7
Section 5.3.9.1
Section 5.3.9.1
Section 5.3.9.2
MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR
DATASHEET
for a description of LED modes.
16
for information on the ADDRESS options.
for information on the ADDRESS options.
for information on the MODE options.
DESCRIPTION
DESCRIPTION
Section
4.9, this pin is sampled during the
SMSC LAN8710/LAN8710i
®
Technology in a Small Footprint
Datasheet