LAN8710A-EZK SMSC, LAN8710A-EZK Datasheet - Page 22

• Manufacturer Part Number: LAN8710A-EZK
• Description: TXRX ETHERNET 10/100 MII/RMII
• Manufacturer: SMSC
• Type: Transceiverr

Specifications of LAN8710A-EZK

• Number Of Drivers/receivers: 4/4
• Protocol: MII, RMII
• Voltage - Supply: 1.6 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1079; LAN8710A-EZK

Revision 1.0 (04-15-09)
4.2.6
4.3
4.3.1
4.3.2
M A C
125 M bps S erial
100M Phase Lock Loop (PLL)
The receive data path is shown in
100M Receive Input
The MLT-3 from the cable is fed into the transceiver (on inputs RXP and RXN) via a 1:1 ratio
transformer. The ADC samples the incoming differential signal at a rate of 125M samples per second.
Using a 64-level quanitizer it generates 6 digital bits to represent each sample. The DSP adjusts the
gain of the ADC according to the observed signal levels such that the full dynamic range of the ADC
can be used.
Equalizer, Baseline Wander Correction and Clock and Data Recovery
The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates
for phase and amplitude distortion caused by the physical channel consisting of magnetics, connectors,
and CAT- 5 cable. The equalizer can restore the signal for any good-quality CAT-5 cable between 1m
and 150m.
If the DC content of the signal is such that the low-frequency components fall below the low frequency
pole of the isolation transformer, then the droop characteristics of the transformer will become
significant and Baseline Wander (BLW) on the received signal will result. To prevent corruption of the
received data, the transceiver corrects for BLW and can receive the ANSI X3.263-1995 FDDI TP-PMD
defined “killer packet” with no bit errors.
The 100M PLL generates multiple phases of the 125MHz clock. A multiplexer, controlled by the timing
unit of the DSP, selects the optimum phase for sampling the data. This is used as the received
recovered clock. This clock is used to extract the serial data from the received signal.
100Base-TX Receive
The 100M PLL locks onto reference clock and generates the 125MHz clock used to drive the 125
MHz logic and the 100Base-Tx Transmitter.
R M II 50M hz by 2 bits
M II 25 M hz by 4 bits
E xt R ef_C LK (for R M II only)
or
(for M II only)
TX _C LK
C onverter
M LT-3
N R ZI
Figure 4.2 Receive Data Path
M agnetics
M II/R M II
MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR
N R ZI
DATASHEET
Figure
4.2. Detailed descriptions are given below.
22
C onverter
P LL
by 4 bits
25M H z
M LT -3
M LT -3
E ncoder
4B /5B
M LT -3
R J45
25M H z by
D river
5 bits
Tx
M LT-3
SMSC LAN8710/LAN8710i
®
Technology in a Small Footprint
S cram bler
and P IS O
C A T-5
Datasheet