ADV7391BCPZ Analog Devices Inc, ADV7391BCPZ Datasheet - Page 51

• Manufacturer Part Number: ADV7391BCPZ
• Description: IC ENCODER VIDEO W/DAC 32-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7391BCPZ

• Applications: Set-Top Boxes, Video Players, Displays
• Voltage - Supply, Analog: 2.6 V ~ 3.46 V
• Voltage - Supply, Digital: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Supply Voltage Range: 1.71V To 1.89V
• Operating Temperature Range: -40°C To +85°C
• Tv / Video Case Style: LFCSP
• No. Of Pins: 32
• Svhc: No SVHC (18-Jun-2010)
• Operating Temperature Max: 85°C
• Operating: RoHS Compliant
• Input Format: Digital
• Output Format: Analogue
• Dac Resolution: 10bit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADV7391EBZ - BOARD EVAL FOR ADV7391 ENCODER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SD VCR FF/RW SYNC
Subaddress 0x82, Bit 5
In DVD record applications where the encoder is used with a
decoder, the VCR FF/RW sync control bit can be used for non-
standard input video, that is, in fast forward or rewind modes.
In fast forward mode, the sync information at the start of a new
field in the incoming video usually occurs before the correct
number of lines/fields is reached. In rewind mode, this sync
signal usually occurs after the total number of lines/fields is
reached. Conventionally, this means that the output video has
corrupted field signals because one signal is generated by the
incoming video and another is generated when the internal
line/field counters reach the end of a field.
When the VCR FF/RW sync control is enabled (Subaddress 0x82,
Bit 5), the line/field counters are updated according to the
incoming VSYNC signal and when the analog output matches
1
2
3
4
5
FOR EXAMPLE, VCR OR CABLE.
F
SEQUENCE BIT
RESET ADV739x DDS.
REFER TO THE ADV7390/ADV7391 AND ADV7392/ADV7393 INPUT CONFIGURATION TABLES FOR PIXEL DATA PIN ASSIGNMENTS.
F
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE
SC
SC
RTC
PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV73xx F
NO F
F
PLL INCREMENTS BITS[21:0] PLUS BITS[0:9] OF SUBCARRIER FREQUENCY REGISTERS.
SC
307
307
RESET APPLIED
Figure 66. SD Subcarrier Frequency Lock Timing and Connections Diagram (Subaddress 0x84, Bits [2:1] = 11)
SC
H/L TRANSITION
COUNT START
COMPOSITE
RESET APPLIED
VIDEO
TIME SLOT 01
Figure 65. SD Subcarrier Phase Reset Timing Diagram (Subaddress 0x84, Bits [2:1] = 01)
128
1
DISPL AY
DISPLAY
310
310
LOW
ADV7403
VIDEO
DECODER
13
LLC1
SUBCARRIER
14 BITS
PHASE
P19 TO
SFL
P10
14
0
4 BITS
RESERVED
313
313
START OF FIELD 4 OR 8
START OF FIELD 4 OR 8
21
19
Rev. B | Page 51 of 108
CLKIN
SFL
PIXEL PORT
SAMPLE
VALID
ADV739x
F
SC
SC
the incoming VSYNC signal. This control is available in all
slave-timing modes except Slave Mode 0.
VERTICAL BLANKING INTERVAL
Subaddress 0x31, Bit 4; Subaddress 0x83, Bit 4
The ADV739x is able to accept input data that contains vertical
blanking interval (VBI) data (such as CGMS, WSS, VITS) in
SD, ED, and HD modes.
If VBI is disabled (Subaddress 0x31, Bit 4 for ED/HD; Subaddress
0x83, Bit 4 for SD), VBI data is not present at the output and the
entire VBI is blanked. These control bits are valid in all master
and slave timing modes.
For the SMPTE 293M (525p) standard, VBI data can be inserted
on Line 13 to Line 42 of each frame or on Line 6 to Line 43 for
the ITU-R BT.1358 (625p) standard. VBI data can be present on
Line 10 to Line 20 for NTSC and on Line 7 to Line 22 for PAL.
PLL INCREMENT
DDS REGISTER IS
5
ADV7390/ADV7391/ADV7392/ADV7393
INVALID
SAMPLE
DAC 1
DAC 2
DAC 3
2
SEQUENCE
8/LINE
LOCKED
CLOCK
F
320
320
SC
F
SC
PHASE = FIELD 4 OR 8
0
BIT
PHASE = FIELD 1
3
6768
5 BITS
RESERVED
F
SC
RESERVED
RESET BIT
RESET PULSE
4