ADV7391BCPZ Analog Devices Inc, ADV7391BCPZ Datasheet - Page 82

• Manufacturer Part Number: ADV7391BCPZ
• Description: IC ENCODER VIDEO W/DAC 32-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7391BCPZ

• Applications: Set-Top Boxes, Video Players, Displays
• Voltage - Supply, Analog: 2.6 V ~ 3.46 V
• Voltage - Supply, Digital: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Supply Voltage Range: 1.71V To 1.89V
• Operating Temperature Range: -40°C To +85°C
• Tv / Video Case Style: LFCSP
• No. Of Pins: 32
• Svhc: No SVHC (18-Jun-2010)
• Operating Temperature Max: 85°C
• Operating: RoHS Compliant
• Input Format: Digital
• Output Format: Analogue
• Dac Resolution: 10bit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADV7391EBZ - BOARD EVAL FOR ADV7391 ENCODER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADV7390/ADV7391/ADV7392/ADV7393
Mode 1—Master Option (Subaddress 0x8A = X X X X X 0 1 1)
In this mode, the ADV739x can generate horizontal synchronization and odd/even field signals. When HSYNC is low, a transition of the
field input indicates a new frame, that is, vertical retrace. The ADV739x automatically blanks all normally blank lines as required by the
CCIR-624 standard. Pixel data is latched on the rising clock edge following the timing signal transitions. HSYNC and FIELD are output
on the HSYNC and VSYNC pins, respectively.
Mode 2— Slave Option (Subaddress 0x8A = X X X X X 1 0 0)
In this mode, the ADV739x accepts horizontal and vertical synchronization signals. A coincident low transition of both HSYNC and
VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The
ADV739x automatically blanks all normally blank lines as required by the CCIR-624 standard. HSYNC and VSYNC are input on the
HSYNC and VSYNC pins, respectively.
HSYNC
HSYNC
FIELD
FIELD
622
309
DISPLAY
DISPLAY
HSYNC
FIELD
PIXEL
DATA
623
310
624
311
EVEN FIELD
ODD FIELD
625
312
Figure 113. SD Timing Mode 1, Odd/Even Field Transitions (Master/Slave)
ODD FIELD
EVEN FIELD
313
1
Figure 112. SD Timing Mode 1, Slave Option, PAL
314
2
315
3
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VERTICAL BLANK
VERTICAL BLANK
316
4
317
5
318
6
319
7
NTSC = 122 × CLOCK/2
PAL = 132 × CLOCK/2
320
Cb
21
Y
334
22
Cr
Y
DISPLAY
335
23
DISPLAY
336