ADV7311KST Analog Devices Inc, ADV7311KST Datasheet
ADV7311KST
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ADV7311KST Summary of contents
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FEATURES High Definition Input Formats 8-/10-, 16-/20-, 24-/30-Bit (4:2:2, 4:4:4) Parallel YCrCb Compliant with: SMPTE 293M (525p) BTA T-1004 EDTV2 (525p) ITU-R BT.1358 (625p/525p) ITU-R BT.1362 (625p/525p) SMPTE 274M (1080i and 25 Hz SMPTE 296M (720p) RGB ...
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ADV7310/ADV7311 DETAILED FEATURES High Definition Programmable Features (720p 1080i) 2 Oversampling (148.5 MHz) Internal Test Pattern Generator (Color Hatch, Black Bar, Flat Field/Frame) Fully Programmable YCrCb to RGB Matrix Gamma Correction Programmable Adaptive Filter Control Programmable Sharpness Filter Control CGMS-A ...
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CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ...
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ADV7310/ADV7311–SPECIFICATIONS V = 2.375–3 1.235 V, R DD_IO REF SET Parameter 1 STATIC PERFORMANCE Resolution Integral Nonlinearity 2 Differential Nonlinearity , +ve 2 Differential Nonlinearity , –ve DIGITAL OUTPUTS Output Low Voltage Output High Voltage, ...
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DYNAMIC SPECIFICATIONS 3040 , R = 300 . All specifications T LOAD Parameter PROGRESSIVE SCAN MODE Luma Bandwidth Chroma Bandwidth SNR HDTV MODE Luma Bandwidth Chroma Bandwidth STANDARD DEFINITION MODE Hue Accuracy Color Saturation Accuracy Chroma Nonlinear Gain Chroma Nonlinear ...
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ADV7310/ADV7311 TIMING SPECIFICATIONS R = 300 . All specifications LOAD MIN MAX Parameter 1 MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth SCLOCK Low Pulsewidth Hold Time (Start Condition Setup Time (Start ...
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CLKIN_A P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK Y9–Y0 C9–C0 CONTROL OUTPUTS t = CLOCK HIGH TIME CLOCK LOW TIME DATA SETUP TIME DATA HOLD TIME 12 Figure 1. HD Only 4:2:2 Input ...
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ADV7310/ADV7311 CLKIN_A P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK Y9–Y0 C9–C0 S9–S0 CONTROL OUTPUTS t = CLOCK HIGH TIME CLOCK LOW TIME DATA SETUP TIME DATA HOLD TIME 12 Figure 3. HD RGB ...
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CLKIN_A P_VSYNC, CONTROL P_HSYN C, INPUTS P_BLANK Y9–Y0 CONTROL OUTPUTS t = CLOCK HIGH TIME CLOCK LOW TIME DATA SETUP TIME DATA HOLD TIME 12 10-Bit Interleaved at 54 MHz HSYNC ...
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ADV7310/ADV7311 CLKIN_B P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK Y9–Y0 Y0 C9–C0 Cb0 CLKIN_A t S_HSYNC, CONTROL S_VSYNC, INPUTS S_BLANK S9–S0 Cb0 Figure 8. HD 4:2:2 and SD (10-Bit) Simultaneous Input Mode [Input Mode 101: SD Oversampled] [Input Mode 110: HD Oversampled] ...
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CLKIN_B P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK Cb0 Y9– CLKIN_A S_HSYNC, CONTROL S_VSYNC, INPUTS S_BLANK S9–S0 Cb0 Figure 10. PS (10-Bit) and SD (10-Bit) Simultaneous Input Mode [Input Mode 100] CLKIN_A t 9 S_HSYNC, CONTROL S_VSYNC, INPUTS S_BLANK ...
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ADV7310/ADV7311 CLKIN_A t 9 S_HSYNC, CONTROL S_VSYNC, INPUTS S_BLANK S9–S0/Y9–Y0* C9–C0 CONTROL OUTPUTS *SELECTED BY ADDRESS 0x01 BIT 7 Figure 12. 20-/16-Bit SD Only Pixel Input Mode [Input Mode 000] P_HSYNC P_VSYNC P_BLANK Y9–Y0 C9– CLKCYCLES FOR ...
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P_HSYNC P_VSYNC P_BLANK Y9– CLKCYCLES FOR 525p CLKCYCLES FOR 625p AS RECOMMENDED BY STANDARD b(MIN) = 244 CLKCYCLES FOR 525p b(MIN) = 264 CLKCYCLES FOR 625p Figure 14. PS 4:2:2 1 S_HSYNC S_VSYNC PAL ...
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... This means that the electroplated Sn coating can be soldered with Sn/Pb solder pastes at conventional reflow temperatures of 220°C to 235°C. Model ADV7310KST ADV7311KST EVAL-ADV7310EB Evaluation Board EVAL-ADV7311EB Evaluation Board *Analog output short circuit to any power supply or common can indefinite duration. ...
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Mnemonic Input/Output Function DGND G Digital Ground. AGND G Analog Ground. CLKIN_A I Pixel Clock Input for HD (74.25 MHz Only, PS Only (27 MHz), SD Only (27 MHz). CLKIN_B I Pixel Clock Input. Requires a 27 MHz reference clock ...
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ADV7310/ADV7311 MPU PORT DESCRIPTION The ADV7310/ADV7311 support a 2-wire serial (I ible) microprocessor bus driving multiple peripherals. Two inputs, serial data (SDA) and serial clock (SCL), carry information between any device connected to the bus and the ADV7310/ ADV7311. Each ...
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WRITE S SLAVE ADDR A(S) SEQUENCE LSB = 0 READ S SLAVE ADDR A(S) SEQUENCE S = START BIT P = STOP BIT REGISTER ACCESSES The MPU can write to or read from all of the registers of the ADV7310/ADV7311 ...
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ADV7310/ADV7311 SR7– SR0 Register Bit Description 00h Power Mode Sleep Mode. With this Register control enabled, the current consumption is reduced to µA level. All DACs and the internal 2 PLL cct are disabled registers can be read ...
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SR7– SR0 Register Bit Description 02h Mode Register 0 Reserved Test Pattern Black Bar RGB Matrix 1 Sync on RGB RGB/YUV Output SD Sync HD Sync 03h RGB Matrix 0 04h RGB Matrix 1 05h RGB Matrix 2 06h RGB ...
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ADV7310/ADV7311 SR7– SR0 Register Bit Description 10h HD Mode HD Output Standard Register 1 HD Input Control Signals HD 625p HD 720p HD BLANK Polarity HD Macrovision for 525p/625p 11h HD Mode HD Pixel Data Valid Register 2 HD Test ...
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SR7– SR0 Register Bit Description 13h HD Mode HD Cr/Cb Sequence Register 4 Reserved HD Input Format Sinc Filter on DAC Reserved HD Chroma SSAF HD Chroma Input HD Double Buffering 14h HD Mode HD Timing Reset ...
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ADV7310/ADV7311 SR7– SR0 Register Bit Description 16h HD Y Level* 17h HD Cr Level* 18h HD Cb Level* 19h Reserved 1Ah Reserved 1Bh Reserved 1Ch Reserved 1Dh Reserved 1Eh Reserved 1Fh Reserved 20h HD Sharpness Filter HD Sharpness Filter Gain ...
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SR7– SR0 Register Bit Description 38h HD Adaptive Filter HD Adaptive Filter Gain 1 Value A Gain 1 HD Adaptive Filter Gain 1 Value B 39h HD Adaptive Filter HD Adaptive Filter Gain 2 Value A Gain 2 HD Adaptive ...
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ADV7310/ADV7311 SR7– SR0 Register Bit Description 3Eh Reserved 3Fh Reserved 40h SD Mode Register 0 SD Standard SD Luma Filter SD Chroma Filter 41h Reserved 42h SD Mode Register 1 SD PrPb SSAF SD DAC Output 1 SD DAC Output ...
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SR7– SR0 Register Bit Description 44h SD Mode SD VSYNC-3H Register 3 SD RTC/TR/SCR SD Active Video Length SD Chroma SD Burst SD Color Bars SD DAC Swap 45h Reserved 46h Reserved 47h SD Mode SD PrPb Scale Register 4 ...
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ADV7310/ADV7311 SR7– SR0 Register Bit Description 4Ah SD Timing SD Slave/Master Mode Register 0 SD Timing Mode SD BLANK Input SD Luma Delay SD Min. Luma Value SD Timing Reset SD HSYNC Width 4Bh SD Timing Register 1 SD HSYNC ...
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SR7– SR0 Register Bit Description 59h SD CGMS/WSS 0 SD CGMS Data SD CGMS CRC SD CGMS on Odd Fields SD CGMS on Even Fields SD WSS 5Ah SD CGMS/WSS 1 SD CGMS/WSS Data 5Bh SD CGMS/WSS 2 SD CGMS/WSS ...
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ADV7310/ADV7311 SR7– SR0 Register Bit Description 65h SD DNR 2 DNR Input Select DNR Mode DNR Block Offset 66h SD Gamma A SD Gamma Curve A Data Points 67h SD Gamma A SD Gamma Curve A Data Points 68h SD ...
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SR7- SR0 Register Bit Description 7Dh Reserved 7Eh Reserved 7Fh Reserved 80h Macrovision MV Control Bits 81h Macrovision MV Control Bits 82h Macrovision MV Control Bits 83h Macrovision MV Control Bits 84h Macrovision MV Control Bits 85h Macrovision MV Control ...
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ADV7310/ADV7311 INPUT CONFIGURATION When 10-bit input data is applied, the following bits must be set to 1: Address 0x7C, Bit 1 (Global 10-Bit Enable) Address 0x13, Bit 2 (HD 10-Bit Enable) Address 0x48, Bit 4 (SD 10-Bit Enable) Note that ...
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ADV7310/ ADV7311 S_VSYNC 3 S_HSYNC S_BLANK SDTV 27MHz DECODER CLKIN_A YCrCb 10 S[9:0] HDTV DECODER CrCb 10 1080i C[9: Y[9:0] 720p P_VSYNC 3 P_HSYNC P_BLANK 74.25MHz CLKIN_B Figure 25. Simultaneous HD and SD Input If in simultaneous ...
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ADV7310/ADV7311 Input Format Total Bits ITU-R BT.656 Only 8 [27 MHz clock] 10 [27 MHz clock] 8 [54 MHz clock] 10 [54 MHz clock HDTV Only ...
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OUTPUT CONFIGURATION The tables below demonstrate what output signals are assigned to the DACs when the control bits are set accordingly. RGB/YUV Output SD DAC Output 1 02h, Bit 5 42h, Bit ...
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ADV7310/ADV7311 TIMING MODES HD Async Timing Mode [Subaddress 10h, Bit 3, 2] For any input data that does not conform to the standards select- able in input mode, Subaddress 10h, asynchronous timing mode can be used to interface to the ...
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P_HSYNC P_VSYNC P_BLANK* 1 → → → → → *When async ...
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ADV7310/ADV7311 SD Real-Time Control, Subcarrier Reset, and Timing Reset [Subaddress 44h, Bit 2, 1] Together with the RTC_SCR_TR pin and SD Mode Register 3 [Address 44h, Bit 1, 2], the ADV7310/ADV7311 can be used in (a) timing reset mode, (b) ...
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Reset Sequence A reset is activated with a high-to-low transition on the RESET pin [Pin 33] according to the timing specifications. The ADV7310/ ADV7311 will revert to the default output configuration. Figure 32 illustrates the RESET sequence timing. SD VCR ...
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ADV7310/ADV7311 Vertical Blanking Interval The ADV7310/ADV7311 accept input data that contains VBI data [CGMS, WSS, VITS, and so on and HD modes. For SMPTE 293M [525p] standards, VBI data can be inserted on Lines ...
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FILTER SECTION Table VI shows an overview of the programmable filters available on the ADV7310/ADV7311. Table VI. Selectable Filters Filter Subaddress SD Luma LPF NTSC 40h SD Luma LPF PAL 40h SD Luma Notch NTSC 40h SD Luma Notch PAL ...
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ADV7310/ADV7311 SD Internal Filter Response [Subaddress 40h; Subaddress 42, Bit 0] The Y filter supports several different frequency responses including two low-pass responses, two notch responses, an extended (SSAF) response with or without gain boost attenuation, a CIF response, and ...
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Typical Performance Characteristics–ADV7310/ADV7311 PROG SCAN Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4 0 –10 –20 –30 –40 –50 –60 –70 – 100 120 FREQUENCY (MHz) TPC 1. PS—UV 8 × Oversampling Filter (Linear) PROG ...
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ADV7310/ADV7311 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) TPC 7. Luma NTSC Low-Pass Filter 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) TPC 8. Luma PAL Low-Pass ...
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FREQUENCY (MHz) TPC 13. Luma SSAF Filter—Programmable Responses – FREQUENCY (MHz) TPC 14. Luma SSAF ...
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ADV7310/ADV7311 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) TPC 19. Chroma 2.0 MHz Low-Pass Filter 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) TPC 20. Chroma 1.3 ...
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COLOR CONTROLS AND RGB MATRIX HD Y Level Level Level [Subaddress 16h–18h] Three 8-bit registers at Address 16h, 17h, 18h are used to program the output color of the internal HD test pattern generator ...
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ADV7310/ADV7311 SD Hue Adjust Value [Subaddress 60h] The hue adjust value is used to adjust the hue on the composite and chroma outputs. These eight bits represent the value required to vary the hue of the video data, i.e., the ...
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PROGRAMMABLE DAC GAIN CONTROL DACs A, B, and C are controlled by REG 0A. DACs D, E, and F are controlled by REG 0B. 2 The I C control registers will adjust the output signal gain up or down from ...
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ADV7310/ADV7311 Gamma Correction [Subaddress 24h–37h for HD, Subaddress 66h–79h for SD] Gamma correction is available for SD and HD video. For each standard, there are twenty 8-bit wide registers. They are used to program the gamma correction curves A and ...
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HD SHARPNESS FILTER CONTROL AND ADAPTIVE FILTER CONTROL [Subaddress 20h, 38h–3Dh] There are three filter modes available on the ADV7310/ADV7311: sharpness filter mode and two adaptive filter modes. HD Sharpness Filter Mode To enhance or attenuate the Y signal in ...
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ADV7310/ADV7311 HD Sharpness Filter and Adaptive Filter Application Examples HD Sharpness Filter Application The HD sharpness filter can be used to enhance or attenuate the Y video output signal. The following register settings were used to achieve the results shown ...
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Adaptive Filter Control Application Figures 45 and 46 show typical signals to be processed by the adaptive filter control block. Figure 45. Input Signal to Adaptive Filter Control Figure 46. Output Signal after Adaptive Filter Control The following register settings ...
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ADV7310/ADV7311 SD Digital Noise Reduction [Subaddress 63h, 64h, 65h] DNR is applied to the Y data only. A filter block selects the high frequency, low amplitude components of the incoming signal [DNR input select]. The absolute value of the filter ...
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Coring Gain Border [Address 63h, Bits 3–0] These four bits are assigned to the gain factor applied to border areas. In DNR mode, the range of gain values increments of 1/8. This factor is applied ...
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ADV7310/ADV7311 SD ACTIVE VIDEO EDGE [Subaddress 42h, Bit 7] When the active video edge is enabled, the first three pixels and the last three pixels of the active video on the luma channel are scaled in such a way that ...
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BOARD DESIGN AND LAYOUT CONSIDERATIONS DAC Termination and Layout Considerations The ADV7310/ADV7311 contain an on-board voltage reference. The ADV7310/ADV7311 can be used with an external V (AD1580). The R resistors are connected between the R SET AGND and are used ...
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ADV7310/ADV7311 4.7 H DAC 3 OUTPUT 6.8pF 600 600 6.8pF 4 560 560 Figure 57. Example of Output Filter for PS, 8 × Oversampling DAC OUTPUT 3 470nH 220nH 75 1 300 33pF 82pF 4 Figure 58. Example of Output ...
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PCB Board Layout Considerations The ADV7310/ADV7311 are optimally designed for lowest noise performance, both radiated and conducted noise. To complement the excellent noise performance of the ADV7310/ADV7311 imperative that great care be given to the PC board layout. ...
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ADV7310/ADV7311 V 0 DD_IO 5k 45 COMP1 S0–S9 S_HSYNC 50 S_VSYNC 49 S_BLANK 48 C0–C9 UNUSED INPUTS SHOULD BE GROUNDED Y0–Y9 63 CLKIN_B P_HSYNC 23 P_VSYNC P_BLANK 25 4.7k RESET 33 ...
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APPENDIX 1—COPY GENERATION MANAGEMENT SYSTEM PS CGMS Data Registers 2–0 [Subaddress 21h, 22h, 23h] PS CGMS is available in 525p mode conforming to CGMS-A EIA-J CPR1204-1, transfer method of video ID information using vertical blanking interval (525p system), March 1998, ...
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ADV7310/ADV7311 +700mV 70% 10% 0mV –300mV 5 +100 IRE +70 IRE 0 IRE –40 IRE 11.2 s Figure 63. Standard Definition CGMS Waveform Diagram +700mV REF 70% 10% 0mV –300mV 4T 3.128 s 90ns +700mV REF ...
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APPENDIX 2—SD WIDE SCREEN SIGNALING [Subaddress 59h, 5Ah, 5Bh] The ADV7310/ADV7311 support wide screen signaling (WSS) conforming to the standard. WSS data is transmitted on Line 23. WSS data can be transmitted only when the device is configured in PAL ...
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ADV7310/ADV7311 APPENDIX 3—SD CLOSED CAPTIONING [Subaddress 51h–54h] The ADV7310/ADV7311 support closed captioning conforming to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and ...
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APPENDIX 4—TEST PATTERNS The ADV7310/ADV7311 can generate SD and HD test patterns CH2 200mV M 10 30.6000 s Figure 68. NTSC Color Bars T 2 CH2 200mV M 10 30.6000 s Figure 69. PAL ...
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ADV7310/ADV7311 T 2 CH2 200mV M 4 1.82872ms Figure 74. 525p Field Pattern T 2 CH2 200mV M 4 1.84176ms Figure 75. 625p Field Pattern T 2 CH2 EVEN Figure 76. 525p Black Bar [–35 mV, ...
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The following register settings are used to generate an SD NTSC CVBS output on DAC A: Subaddress 00h 40h 42h 44h 4Ah All other registers are set as normal/default. For PAL CVBS output on DAC A, the same settings are ...
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ADV7310/ADV7311 APPENDIX 5—SD TIMING MODES [Subaddress 4Ah] Mode 0 (CCIR-656)—Slave Option (Timing Register 0 TR0 = The ADV7310/ADV7311 is controlled by the SAV (start active video) and EAV (end active video) time ...
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Mode 0 (CCIR-656)—Master Option (Timing Register 0 TR0 = The ADV7310/ADV7311 generates H, V, and F signals required for the SAV (start active video) and EAV (end active video) time codes in ...
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ADV7310/ADV7311 ANALOG VIDEO Mode 1—Slave Option (Timing Register 0 TR0 = this mode, the ADV7310/ADV7311 accept horizontal sync and odd/even field signals. A transition of the field input ...
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Mode 1—Master Option (Timing Register 0 TR0 = this mode, the ADV7310/ADV7311 can generate horizontal sync and odd/even field signals. A transition of the field input when HSYNC is low indicates ...
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ADV7310/ADV7311 Mode 2— Slave Option (Timing Register 0 TR0 = this mode, the ADV7310/ADV7311 accepts horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC inputs indicates ...
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Mode 2—Master Option (Timing Register 0 TR0 = this mode, the ADV7310/ADV7311 can generate horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the ...
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ADV7310/ADV7311 Mode 3—Master/Slave Option (Timing Register 0 TR0 = this mode, the ADV7310/ADV7311 accept or generate horizon- tal sync and odd/even field ...
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APPENDIX 6—HD TIMING FIELD 1 1124 1125 P_VSYNC P_HSYNC FIELD 2 561 562 P_VSYNC P_HSYNC REV. A VERTICAL BLANKING INTERVAL VERTICAL BLANKING INTERVAL 563 564 565 566 567 568 569 Figure 91. 1080i ...
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ADV7310/ADV7311 APPENDIX 7—VIDEO OUTPUT LEVELS HD YPrPb Output Levels EIA-770.2, STANDARD FOR Y INPUT CODE 940 64 EIA-770.2, STANDARD FOR Pr/Pb 960 512 64 Figure 92. EIA 770.2 Standard Output Signals (525p/625p) EIA-770.1, STANDARD FOR Y INPUT CODE 940 64 ...
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RGB Output Levels 700mV 550mV 300mV 700mV 300mV 700mV 300mV Figure 96. HD RGB Output Levels 700mV 550mV 300mV 0mV 700mV 300mV 0mV 700mV 300mV 0mV Figure 97. HD RGB Output Levels—RGB Sync Enabled REV. A 300mV 550mV 300mV 550mV ...
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ADV7310/ADV7311 YUV Output Levels 280mV 220mV 160mV 60mV Figure 100. U Levels—NTSC 280mV 220mV 160mV 60mV Figure 101. U Levels—PAL 200mV 1260mV 1000mV 140mV Figure 102. U Levels—NTSC 332mV 110mV 332mV 110mV 2150mV 900mV –76– 2150mV 200mV 1260mV 1000mV 900mV ...
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VOLTS IRE:FLT 0 APL = 44.5% 525 LINE NTSC SLOW CLAMP TO 0.00V AT 6.72 s VOLTS IRE:FLT 0.4 0.2 0 –0.2 –0.4 0 NOISE REDUCTION: 15.05dB APL NEEDS SYNC-SOURCE. 525 LINE NTSC NO FILTERING SLOW CLAMP TO ...
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ADV7310/ADV7311 VOLTS IRE:FLT 0.6 0.4 0.2 0 –0.2 10 NOISE REDUCTION: 15.05dB APL = 44.3% 525 LINE NTSC NO FILTERING SLOW CLAMP TO 0.00 AT 6.72 s VOLTS 0.6 0.4 0.2 0 –0.2 0 NOISE REDUCTION: 0.00dB APL = 39.1% ...
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VOLTS 0.5 0 –0.5 10 APL NEEDS SYNC-SOURCE. 625 LINE PAL NO FILTERING SLOW CLAMP TO 0.00 AT 6.72 s VOLTS 0 APL NEEDS SYNC-SOURCE. 625 LINE PAL NO FILTERING SLOW CLAMP TO 0.00 AT 6.72 s REV. ...
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ADV7310/ADV7311 APPENDIX 8—VIDEO STANDARDS SMPTE 274M ANALOG WAVEFORM 4T EAV CODE INPUT PIXELS CLOCK SAMPLE NUMBER 2112 2116 2156 FVH* = FVH AND PARITY BITS SAV/EAV: LINE 1–562 ...
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ACTIVE VIDEO 522 523 524 525 ACTIVE VIDEO 622 623 624 625 747 748 749 750 FIELD 1 1124 1125 FIELD 2 561 562 REV. A VERTICAL BLANK Figure 114. SMPTE 293M ...
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ADV7310/ADV7311 10 1. 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90 CCW OUTLINE DIMENSIONS 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64) Dimensions shown in millimeters 0.75 0.60 1.60 MAX 0. SEATING PIN 1 ...
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Revision History Location 8/03—Data Sheet changed from REV REV. A. Addition to Standards Directly Supported Table . . . . . . . . . . . . . . . . . . . . . . ...
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