ADV7185KST Analog Devices Inc, ADV7185KST Datasheet - Page 14

• Manufacturer Part Number: ADV7185KST
• Description: IC VIDEO DECODER NTSC 80LQFP
• Manufacturer: Analog Devices Inc
• Type: Decoderr

Specifications of ADV7185KST

• Rohs Status: RoHS non-compliant
• Applications: DVD-RAM, Projectors, TV
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LQFP
• Pin Count: 80
• Voltage - Supply, Analog: -
• Voltage - Supply, Digital: -
• Lead Free Status / RoHS Status: Not Compliant

ADV7185
OUTPUT INTERFACE
Mode Selection Overview
The ADV7185 supports three output interfaces: LLC-compatible
synchronous pixel interface, the CAPI interface, and SCAPI
interface. When the part is configured in the synchronous pixel
interface mode, pixel and control data are output synchronous
with LLC1 (8-bit or 10-bit mode) or LLC2 (16-bit or 20-bit
mode). In this mode, control and timing information for field,
vertical blanking, and horizontal blanking identification may
also be encoded as control codes.
When configured in CAPI or SCAPI mode, only the active pixel
data is output synchronous with the CLKIN (asynchronous
FIFO clock). The pixels are output via a 512-pixel deep 20-bit wide
FIFO. HACTIVE and VACTIVE are output on independent
pins. HACTIVE will be active during the active viewable period
of a video line and VACTIVE will be active during the active
viewable period of a video field. CAPI and SCAPI modes will
P[19–12][7:0]
PIXEL DATA
PIXEL DATA
P[9–2][7:0]
LLC1
LLC2
Figure 20. Synchronous Pixel Interface, 16-Bit Example
00
FF
SAV
SAV
XY
00
SAV
SAV
Cb0
Y0
–14–
always output data in 16-bit or 20-bit mode, so this mode of
operation cannot be used when an 8-bit or 10-bit output interface
is required. After power-up, the ADV7185 will default to the
LLC-compatible 8-bit CCIR656 4:2:2 @ LLC.
Synchronous Pixel Interface
When the output is configured for an 8-bit pixel interface, the
data is output on the pixel output port P[12:19]; 10-bit pixel
interface uses P[13:19]. In this mode, 10/8 bits of chrominance
data will precede 8/10 bits of luminance data. New pixel data
is output on the pixel port after each rising edge of LLC1. When
the output is configured for a 16-bit pixel interface, the lumi-
nance data is output on P[19:12] and the chrominance data on
P[2:9]. In this mode the data is output with respect to LLC2.
20-bit pixel operation will use P[19:10] for luminance data and
P[9:0] for chrominance data; as with the 16-bit mode data is
output with respect to LLC2. Figure 20 shows the basic timing
relationship for this mode.
Cr0
Y1
Cb1
Y2
Y3
Cr1
Cb2
Y4
REV. 0