ADV7185KST Analog Devices Inc, ADV7185KST Datasheet - Page 9

• Manufacturer Part Number: ADV7185KST
• Description: IC VIDEO DECODER NTSC 80LQFP
• Manufacturer: Analog Devices Inc
• Type: Decoderr

Specifications of ADV7185KST

• Rohs Status: RoHS non-compliant
• Applications: DVD-RAM, Projectors, TV
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LQFP
• Pin Count: 80
• Voltage - Supply, Analog: -
• Voltage - Supply, Digital: -
• Lead Free Status / RoHS Status: Not Compliant

GENERAL DESCRIPTION
The ADV7185 is an integrated video decoder that automatically
detects and converts a standard analog baseband television sig-
nal compatible with worldwide standards NTSC or PAL into
4:2:2 or 4:1:1 component video data compatible with 16-/8-bit
CCIR601/CCIR656 or 10-/20-bit extended standards.
The advanced and highly flexible digital output interface
enables performance video decoding and conversion in both
frame-buffer-based and line-locked, clock-based systems. This
makes the device ideally suited for a broad range of applica-
tions with diverse analog video characteristics, including
tape-based sources, broadcast sources, security/surveillance
cameras, and professional systems.
Fully integrated line stores enable real-time horizontal and
vertical scaling of captured video down to icon size. The 12-bit
accurate A/D conversion provides professional quality SNR
performance. This allows true 8-bit resolution in the 8-bit out-
put mode, and broadcast quality in the 10-bit extended mode.
The six analog input channels accept standard composite or
advanced component video including S-video and YCrCb
video signals in an extensive number of combinations. AGC
and clamp restore circuitry allow an input video signal peak-
to-peak range of 0.5 V up to 2 V. Alternatively, these can be
bypassed for manual settings.
The fixed 27 MHz clocking of the ADCs and data path for all
modes allows very precise and accurate sampling and digital
filtering. The line-locked clock output allows the output data
rate, timing signals, and output clock signals to be synchronous,
asynchronous, or line-locked even with ± 5% line length varia-
tion. The output control signals allow glueless interface
connection in almost any application.
The ADV7185 modes are set up over a 2-wire serial bidirec-
tional port (I
The ADV7185 is fabricated in a 5 V CMOS process. Its mono-
lithic CMOS construction ensures greater functionality with
lower power dissipation.
The ADV7185 is packaged in a small 80-pin LQFP package.
REV. 0
(FEATURES continued from page 1)
Simplified Digital Interface
On-Board Digital FIFO
Optimized Programmable Video Source Modes:
Integrated On-Chip Video Timing Generator
Synchronous or Asynchronous Output Timing
Line-Locked Clock Output
Closed Captioning Passthrough Operation
Vertical Blanking Interval Support
Power-Down Mode
2-Wire Serial MPU Interface (I
5 V Analog 3.3 V Digital Supply Operation
80-Lead LQFP Package
Broadcast TV
VCR/Camcorder
Security/Surveillance
2
C-compatible).
2
C-Compatible)
–9–
ANALOG INPUT PROCESSING
The ADV7185 has six analog video input channels. These six
channels can be arranged in a variety of configurations to support
up to six CVBS input signals, three S-video input signals and two
YCrCb component analog video input signals. The INSEL[3:0]
bits control the input type and channel selected. The analog front
end includes three clamp circuits for dc restore. There are three
sample-and-hold amplifiers prior to the ADC that are used to
enable simultaneous sampling of up to three channels in a
YCrCb input mode. Two 12-bit ADCs are used for sampling.
The entire analog front end is fully differential which ensures that
the video is captured to the highest quality possible. This is very
important in highly integrated systems such as video decoders.
Figure 5 shows the analog front end section of the ADV7185.
CLAMPING
The clamp control on the ADV7185 consists of a digitally
controlled analog current and voltage clamp and a digitally
controlled digital clamp circuit. The coupling capacitor on each
channel is used to store and filter the clamping voltage. A digital
controller controls the clamp up and down current sources that
charge the capacitor on every line. Four current sources are
used in the current clamp control, two large current sources are
used for coarse clamping, and two small current sources are
used for fine clamping. The voltage clamp, if enabled, is only
used on startup or if a channel is switched; this clamp pulls the
video into the midrange of the ADC, which results in faster
clamping and faster lock-in time for the decoder. The fourth
clamp controller is fully digital and clamps the ADC output
data, which results in extremely accurate clamping. It also has
the added advantage of being fully digital, which results in very
fast clamp timing and makes the entire clamping process very
robust in terms of handling large amounts of hum that can be
present on real-world video signals.
In S-video mode there are two clamp controllers used to sepa-
rately control the luminance clamping and the chrominance
NOTES
ANALOG SIGNAL PATH KEPT FULLY DIFFERENTIAL ADCs: 12-BIT
ACCURATE; 12dB GAIN RANGE
1
2
CLAMP BLOCKS CONTAIN A SET OF CURRENT SOURCES FOR DC
PIPELINED
CLAMP V
RESTORATION; U AND V HAVE ONLY HALF BANDWIDTH (SAMPLED
SIMULTANEOUSLY, CONVERTED SEQUENTIALLY)
Figure 5. Analog Front End Block Diagram
SHA
2
1
MUX
MUX 6CVBS 3YC 2YUV
CLAMP U
SHA
2
1
CLAMP Y
SHA
2
1
Y ADC
C ADC
ADV7185
2
2
12
12