ADV7181BCP Analog Devices Inc, ADV7181BCP Datasheet - Page 15

• Manufacturer Part Number: ADV7181BCP
• Description: IC VIDEO DECODER NTSC 64-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7181BCP

• Applications: Recorders, Set-Top Boxes
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Adc/dac Resolution: 9b
• Screening Level: Industrial
• Package Type: LFCSP EP
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: EVAL-ADV7181BEB - BOARD EVALUATION FOR ADV7181
• Lead Free Status / RoHS Status: Compliant, Contains lead / RoHS non-compliant

GLOBAL CONTROL REGISTERS
Register control bits listed in this section affect the whole chip.
POWER-SAVE MODES
Power-Down
The digital core of the ADV7181B can be shut down by using a
pin ( PWRDN ) and a bit (PWRDN); see below. The PDBP
controls which of the two has the higher priority. By default, the
pin ( PWRDN ) is given priority. This allows the user to have the
ADV7181B powered down by default.
PDBP, Address 0x0F[2]
When PDBP is 0 (default), the digital core power is controlled
by the PWRDN pin (the bit is disregarded).
When PDBP is 1, the bit has priority (the pin is disregarded).
PWRDN, Address 0x0F[5]
Setting the PWRDN bit switches the ADV7181B into a chip-
wide power-down mode. The power-down stops the clock from
entering the digital section of the chip, thereby freezing its
operation. No I
PWRDN bit also affects the analog blocks and switches them
into low current modes. The I
remains operational in power-down mode.
The ADV7181B leaves the power-down state if the PWRDN bit
is set to 0 (via I
RESET pin.
PDBP must be set to 1 for the PWRDN bit to power down the
ADV7181B.
When PWRDN is 0 (default), the chip is operational.
When PWRDN is 1, the ADV7181B is in chip-wide power-down.
ADC Power-Down Control
The ADV7181B contains three 9-bit ADCs (ADC 0, ADC 1,
and ADC 2). If required, it is possible to power down each ADC
individually.
The ADCs should be powered down when in:
•
•
CVBS mode. ADC 1 and ADC 2 should be powered down
to save on power consumption.
S-Video mode. ADC 2 should be powered down to save on
power consumption.
2
2
C), or if the overall part is reset using the
C bits are lost during power-down. The
2
C interface is unaffected and
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PWRDN_ADC_0, Address 0x3A[3]
When PWRDN_ADC_0 is 0 (default), the ADC is in normal
operation.
When PWRDN_ADC_0 is 1, ADC 0 is powered down.
PWRDN_ADC_1, Address 0x3A[2]
When PWRDN_ADC_1 is 0 (default), the ADC is in normal
operation.
When PWRDN_ADC_1 is 1, ADC 1 is powered down.
PWRDN_ADC_2, Address 0x3A[1]
When PWRDN_ADC_2 is 0 (default), the ADC is in normal
operation (default).
When PWRDN_ADC_2 is 1, ADC 2 is powered down.
RESET CONTROL
Chip Reset (RES), Address 0x0F[7]
Setting this bit, equivalent to controlling the RESET pin on the
ADV7181B, issues a full chip reset. All I
their default values. Note that some register bits do not have a
reset value specified; they keep their last written value. Those
bits are marked as having a reset value of x in the register table.
After the reset sequence, the part immediately starts to acquire
the incoming video signal.
After setting the RES bit (or initiating a reset via the pin), the
part returns to the default mode of operation with respect to its
primary mode of operation. All I
default values, making this bit self-clearing.
Executing a software reset takes approximately 2 ms. However,
it is recommended to wait 5 ms before any further I
performed.
The I
on the ninth clock cycle when chip reset is implemented. See
the MPU Port Description section.
When RES is 0 (default), operation is normal.
When RES is 1, the reset sequence starts.
2
C master controller receives a no acknowledge condition
2
C bits are loaded with their
2
C registers are reset to
ADV7181B
2
C writes are