ADV7181BCP Analog Devices Inc, ADV7181BCP Datasheet - Page 41

• Manufacturer Part Number: ADV7181BCP
• Description: IC VIDEO DECODER NTSC 64-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7181BCP

• Applications: Recorders, Set-Top Boxes
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Adc/dac Resolution: 9b
• Screening Level: Industrial
• Package Type: LFCSP EP
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: EVAL-ADV7181BEB - BOARD EVALUATION FOR ADV7181
• Lead Free Status / RoHS Status: Compliant, Contains lead / RoHS non-compliant

Table 55. Recommended User Settings for NTSC (See Figure 21)
Register
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0xE5
0xE6
0xE7
NVBEGDELO NTSC Vsync Begin Delay on Odd Field,
Address 0xE5[7]
When NVBEGDELO is 0 (default), there is no delay.
Setting NVBEGDELO to 1 delays Vsync going high on an odd
field by a line relative to NVBEG.
NVBEGDELE NTSC Vsync Begin Delay on Even Field,
Address 0xE5[6]
When NVBEGDELE is 0 (default), there is no delay.
Setting NVBEGDELE to 1 delays Vsync going high on an even
field by a line relative to NVBEG.
NOT VALID FOR USER
Register Name
Vsync Field Control 1
Vsync Field Control 2
Vsync Field Control 3
Hsync Pos. Control 1
Hsync Pos. Control 1
Hsync Pos. Control 1
Polarity
NTSV_V_Bit_Beg
NTSC_V_Bit_End
NTSC_F_Bit_Tog
PROGRAMMING
VSYNC BY NVBEG[4:0]
ADVANCE BEGIN OF
ADVANCE BY
NVBEGDELO
ADDITIONAL
DELAY BY
0.5 LINE
VSBHO
1 LINE
YES
Figure 22. NTSC Vsync Begin
1
1
Rev. B | Page 41 of 100
1
VSYNC BEGIN
0
0
NVBEGSIGN
ODD FIELD?
NVBEGSIGN NTSC Vsync Begin Sign, Address 0xE5[5]
Setting NVBEGSIGN to 0 delays the start of Vsync. Set for user
manual programming.
Setting NVBEGSIGN to 1 (default) advances the start of Vsync.
Not recommended for user programming.
NVBEG[4:0] NTSC Vsync Begin, Address 0xE5[4:0]
The default value of NVBEG is 00101, indicating the NTSC
Vsync begin position.
For all NTSC/PAL Vsync timing controls, both the V bit in the
AV code and the Vsync on the VS pin are modified.
0
0
VSYNC BY NVBEG[4:0]
DELAY BEGIN OF
ADVANCE BY
NVBEGDELE
ADDITIONAL
DELAY BY
0
0.5 LINE
VSBHE
1 LINE
NO
1
1
Write
0x1A
0x81
0x84
0x00
0x00
0x7D
0xA1
0x41
0x84
0x06
ADV7181B